{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,22]],"date-time":"2026-09-22T16:22:32Z","timestamp":1790094152899,"version":"4.0.1"},"reference-count":55,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","license":[{"start":{"date-parts":[[2023,9,9]],"date-time":"2023-09-09T00:00:00Z","timestamp":1694217600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"US National Science Foundation","doi-asserted-by":"crossref","award":["CNS-1955353"],"award-info":[{"award-number":["CNS-1955353"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"crossref","award":["3012.001, 3014.001"],"award-info":[{"award-number":["3012.001, 3014.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2023,10,31]]},"abstract":"<jats:p>Recent advances in 2.5D chiplet platforms provide a new avenue for compact scale-out implementations of emerging compute- and data-intensive applications including machine learning. Network-on-Interposer (NoI) enables integration of multiple chiplets on a 2.5D system. While these manycore platforms can deliver high computational throughput and energy efficiency by running multiple specialized tasks concurrently, conventional NoI architectures have a limited computational throughput due to their inherent multi-hop topologies. In this paper, we propose Floret, a novel NoI architecture based on space-filling curves (SFCs). The Floret architecture leverages suitable task mapping, exploits the data flow pattern, and optimizes the inter-chiplet data exchange to extract high performance for multiple types of convolutional neural network (CNN) inference tasks running concurrently. We demonstrate that the Floret architecture reduces the latency and energy up to 58% and 64%, respectively, compared to state-of-the-art NoI architectures while executing datacenter-scale workloads involving multiple CNN tasks simultaneously. Floret achieves high performance and significant energy savings with much lower fabrication cost by exploiting the data-flow awareness of the CNN inference tasks.<\/jats:p>","DOI":"10.1145\/3608098","type":"journal-article","created":{"date-parts":[[2023,9,9]],"date-time":"2023-09-09T13:33:18Z","timestamp":1694266398000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0334-4269","authenticated-orcid":false,"given":"Harsh","family":"Sharma","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, WA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7905-9843","authenticated-orcid":false,"given":"Lukas","family":"Pfromm","sequence":"additional","affiliation":[{"name":"University of Wisconsin Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8759-6959","authenticated-orcid":false,"given":"Rasit Onur","family":"Topaloglu","sequence":"additional","affiliation":[{"name":"Topallabs, Poughkeepsie, NY, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3848-5301","authenticated-orcid":false,"given":"Janardhan Rao","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5045-5535","authenticated-orcid":false,"given":"Umit Y.","family":"Ogras","sequence":"additional","affiliation":[{"name":"University of Wisconsin Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3495-2264","authenticated-orcid":false,"given":"Ananth","family":"Kalyanraman","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5930-8531","authenticated-orcid":false,"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,9,9]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830808"},{"key":"e_1_3_2_3_2","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Stow D.","year":"2017","unstructured":"D. Stow et al. 2017. Cost-Effective design of scalable high-performance systems using active and passive interposers. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)."},{"key":"e_1_3_2_4_2","doi-asserted-by":"crossref","DOI":"10.1109\/66.53188","article-title":"The use and evaluation of yield models in integrated circuit manufacturing","author":"Cunningham J. A.","year":"1990","unstructured":"J. A. Cunningham et al. 1990. The use and evaluation of yield models in integrated circuit manufacturing. IEEE Transaction of Semiconductor Manufacturing (1990).","journal-title":"IEEE Transaction of Semiconductor Manufacturing"},{"key":"e_1_3_2_5_2","unstructured":"International technology roadmap for semiconductors 2.0 2015 edition system integration. Report Ch 1 2015. Semiconductor Industry Association 2015."},{"key":"e_1_3_2_6_2","volume-title":"Proceedings of 57th ACM\/IEEE Design Automation Conference (DAC)","author":"Bharadwaj S.","year":"2020","unstructured":"S. Bharadwaj, J. Yin, B. Beckmann, and T. Krishna. 2020. Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling. In Proceedings of 57th ACM\/IEEE Design Automation Conference (DAC)."},{"issue":"5","key":"e_1_3_2_7_2","article-title":"SIAM: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks","volume":"20","author":"Krishnan G.","year":"2021","unstructured":"G. Krishnan et al. 2021. SIAM: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks. In ACM Transaction of Embedded Computer Systems 20, 5 (2021).","journal-title":"In ACM Transaction of Embedded Computer Systems"},{"key":"e_1_3_2_8_2","volume-title":"Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Shao Y.","year":"2019","unstructured":"Y. Shao et al. 2019. Simba: Scaling deep-learning inference with multi-chip-module-based architecture. In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)."},{"key":"e_1_3_2_9_2","volume-title":"Proceedings of the International Symposium on Computer Architecture (ISCA)","author":"Tan Z.","year":"2021","unstructured":"Z. Tan, H. Cai, R. Dong, and K. Ma. 2021. NN-Baton: DNN workload orchestration and chiplet granularity exploration for multichip accelerators. In Proceedings of the International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3477132.3483590"},{"key":"e_1_3_2_11_2","unstructured":"https:\/\/www.cloudera.com\/content\/dam\/www\/marketing\/resources\/ebooks\/how-to-take-ai-applications-from-concept-to-reality-with-cml-on-aws.pdf.landing.html"},{"key":"e_1_3_2_12_2","volume-title":"Proceedings of the International Conference on Cluster Computing (CLUSTER)","author":"Verma A.","year":"2014","unstructured":"A. Verma, M. Korupolu, and J. Wilkes. 2014. Evaluating job packing in warehouse-scale computing. In Proceedings of the International Conference on Cluster Computing (CLUSTER)."},{"key":"e_1_3_2_13_2","volume-title":"Proceedings of the Pacific-Asia Conference on Knowledge Discovery and Data Mining","author":"Juan D. C.","unstructured":"D. C. Juan, L. Li, H. K. Peng, D. Marculescu, and C. Faloutsos. Beyond Poisson: Modeling inter-arrival time of requests in a datacenter. In Proceedings of the Pacific-Asia Conference on Knowledge Discovery and Data Mining."},{"key":"e_1_3_2_14_2","first-page":"458","volume-title":"Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Jerger N.","year":"2014","unstructured":"N. Jerger, A. Kannan, Z. Li, and G. Loh. 2014. NoC architectures for silicon interposer systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?. In Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 458-470."},{"issue":"4","key":"e_1_3_2_15_2","doi-asserted-by":"crossref","DOI":"10.1109\/JSSC.2019.2960488","article-title":"A 0.32\u2013128 TOPS, scalable Multi-Chip-Module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm","volume":"55","author":"Zimmer B.","year":"2020","unstructured":"B. Zimmer et al. 2020. A 0.32\u2013128 TOPS, scalable Multi-Chip-Module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm. IEEE Journal of Solid-State Circuits 55, 4 (2020).","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_16_2","volume-title":"Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design","author":"Li F.","year":"2022","unstructured":"F. Li et al. 2022. GIA: A reusable general interposer architecture for agile chiplet integration. In Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design."},{"issue":"1","key":"e_1_3_2_17_2","doi-asserted-by":"crossref","DOI":"10.1109\/JSSC.2020.3036341","article-title":"IntAct: A 96-Core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management","volume":"56","author":"Vivet P.","year":"2021","unstructured":"P. Vivet et al. 2021. IntAct: A 96-Core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management. IEEE Journal of Solid-State Circuits 56, 1 (2021).","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3197500"},{"issue":"1","key":"e_1_3_2_19_2","doi-asserted-by":"crossref","DOI":"10.3390\/make1010005","article-title":"A survey of ReRAM-based architectures for processing-in-memory and neural networks","volume":"1","author":"Mittal S.","year":"2019","unstructured":"S. Mittal. 2019. A survey of ReRAM-based architectures for processing-in-memory and neural networks. Machine Learning and Knowledge Extraction 1, 1 (2019).","journal-title":"Machine Learning and Knowledge Extraction"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"e_1_3_2_21_2","volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA)","author":"Song L.","year":"2017","unstructured":"L. Song, X. Qian, H. Li, and Y. Chen. 2017. PipeLayer: A pipelined ReRAM-Based accelerator for deep learning. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA)."},{"key":"e_1_3_2_22_2","first-page":"1","volume-title":"IEEE Symposium on VLSI Circuits","author":"Giordano M.","year":"2021","unstructured":"M. Giordano et al. 2021. CHIMERA: A 0.92 TOPS, 2.2 TOPS\/W Edge AI accelerator with 2 MByte On-Chip foundry resistive RAM for efficient training and inference. In IEEE Symposium on VLSI Circuits. 1\u20132."},{"issue":"20","key":"e_1_3_2_23_2","article-title":"3D-ReG: A 3D ReRAM-based heterogeneous architecture for training deep neural networks","volume":"16","author":"Li B.","year":"2020","unstructured":"B. Li et al. 2020. 3D-ReG: A 3D ReRAM-based heterogeneous architecture for training deep neural networks. In the Journal of Emerging Technology of Computer Systems 16, 20 (2020).","journal-title":"the Journal of Emerging Technology of Computer Systems"},{"key":"e_1_3_2_24_2","volume-title":"Proceedings of the International Symposium on Computer Architecture (ISCA)","author":"Chi P.","year":"2016","unstructured":"P. Chi et al. 2016. PRIME: A novel processing- in-memory architecture for neural network computation in ReRAM-Based main memory. In Proceedings of the International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_3_2_25_2","volume-title":"Proceedings of the 46th International Symposium on Computer Architecture (ISCA)","author":"Imani M.","year":"2019","unstructured":"M. Imani, S. Gupta, Y. Kim, and T. Rosing. 2019. Floatpim: In-memory acceleration of deep neural network training with high precision. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_3_2_26_2","volume-title":"Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design","author":"Ebadollah T.","year":"2022","unstructured":"T. Ebadollah, S. Pasricha, and M. Nikdast. 2022. ReSiPI: A reconfigurable silicon-photonic 2.5 D chiplet network with PCMs for Energy-Efficient Interposer Communication. In Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design."},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2018.2833876"},{"key":"e_1_3_2_28_2","article-title":"Space-filling curves","author":"Sagan H.","year":"2012","unstructured":"H. Sagan. 2012. Space-filling curves. Springer Science & Business Media (2012).","journal-title":"Springer Science & Business Media"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1007\/BF01199431"},{"key":"e_1_3_2_30_2","volume-title":"IBM","author":"Morton G.","year":"1966","unstructured":"G. Morton. 1966. A computer oriented geodetic data base and a new technique in file sequencing. In IBM, Ottawa, Canada, 1966."},{"key":"e_1_3_2_31_2","first-page":"1295","volume-title":"Proceedings of the 26th International Parallel and Distributed Processing Symposium","author":"Xu P.","year":"2012","unstructured":"P. Xu and S. Tirthapura. 2012. A lower bound on proximity preservation by space filling curves. In Proceedings of the 26th International Parallel and Distributed Processing Symposium. 1295\u20131305."},{"key":"e_1_3_2_32_2","volume-title":"Proceedings of the 34th International Conference on Data Engineering (ICDE)","author":"Xu P.","year":"2018","unstructured":"P. Xu, N. Cuong, and S. Tirthapura. 2018. Onion curve: A space filling curve with near-optimal clustering. In 2018). In Proceedings of the 34th International Conference on Data Engineering (ICDE)."},{"key":"e_1_3_2_33_2","volume-title":"Proceedings of the 42nd International Conference on Parallel Processing","author":"DeFord D.","year":"2013","unstructured":"D. DeFord and A. Kalyanaraman. 2013. Empirical analysis of space-filling curves for scientific computing applications. In Proceedings of the 42nd International Conference on Parallel Processing."},{"issue":"5","key":"e_1_3_2_34_2","doi-asserted-by":"crossref","first-page":"794","DOI":"10.1109\/83.499920","article-title":"The metric properties of discrete space-filling curves","volume":"5","author":"Lindenbaum M.","year":"1996","unstructured":"M. Lindenbaum and C. Gotsman. 1996. The metric properties of discrete space-filling curves. IEEE Transactions on Image Processing 5, 5 (1996), 794\u2013797.","journal-title":"IEEE Transactions on Image Processing"},{"issue":"1","key":"e_1_3_2_35_2","doi-asserted-by":"crossref","DOI":"10.1109\/69.908985","article-title":"Analysis of the clustering properties of Hilbert spacefilling curve","volume":"13","author":"Moon B.","year":"2001","unstructured":"B. Moon, H. Jagadish, C. Faloutsos, and J. Saltz. 2001. Analysis of the clustering properties of Hilbert spacefilling curve. IEEE Transactions on Knowledge and Data Engineering 13, 1 (2001).","journal-title":"IEEE Transactions on Knowledge and Data Engineering"},{"key":"e_1_3_2_36_2","volume-title":"Proceedings of the International Conference on Parallel Processing (ICPP'06)","author":"Tirthapura S.","year":"2006","unstructured":"S. Tirthapura, S. Seal, and S. Aluru. 2006. A formal analysis of space filling curves for parallel domain decomposition. In Proceedings of the International Conference on Parallel Processing (ICPP'06)."},{"key":"e_1_3_2_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/93597.98742"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.5555\/523991.938911"},{"key":"e_1_3_2_39_2","volume-title":"Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS) Workshop","author":"Bethel E. W.","year":"2015","unstructured":"E. W. Bethel, D. Camp, D. Donofrio, and M. Howison. 2015. Improving performance of structured-memory, data-intensive applications on multi-core platforms via a space-filling curve memory layout. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS) Workshop."},{"key":"e_1_3_2_40_2","volume-title":"Proceedings of the International Conference on Bioinformatics and Biomedicine","author":"Haque M. M.","year":"2009","unstructured":"M. M. Haque, A. Kalyanaraman, A. Dhingra, N. Abu-Lail, and K. Graybeal. 2009. DNAjig: A new approach for building DNA nanostructures. In Proceedings of the International Conference on Bioinformatics and Biomedicine."},{"issue":"1","key":"e_1_3_2_41_2","doi-asserted-by":"crossref","first-page":"29","DOI":"10.1109\/TC.2009.133","article-title":"Network-on-chip hardware accelerators for biological sequence alignment","volume":"59","author":"Sarkar S.","year":"2009","unstructured":"S. Sarkar, G. R. Kulkarni, P. P. Pande, and A. Kalyanaraman. 2009. Network-on-chip hardware accelerators for biological sequence alignment. IEEE Transactions on Computers 59, 1 (2009), 29\u201341.","journal-title":"IEEE Transactions on Computers"},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.suscom.2013.01.001"},{"key":"e_1_3_2_43_2","doi-asserted-by":"crossref","unstructured":"S. Pati et al. 2023. Computation vs. Communication Scaling for Future Transformers on Future Hardware. In arXiv:2302.02825 2023.","DOI":"10.1109\/IISWC59245.2023.00026"},{"key":"e_1_3_2_44_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-0410-3"},{"key":"e_1_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0288-0"},{"issue":"7","key":"e_1_3_2_46_2","article-title":"NVSim: A Circuit-Level performance, energy, and area model for emerging nonvolatile memory","volume":"31","author":"Dong X.","year":"2012","unstructured":"X. Dong, C. Xu, Y. Xie, and N. Jouppi. 2012. NVSim: A Circuit-Level performance, energy, and area model for emerging nonvolatile memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 7 (2012).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_47_2","doi-asserted-by":"publisher","DOI":"10.5555\/3437539.3437737"},{"issue":"1","key":"e_1_3_2_48_2","article-title":"RAMULATOR: A fast and extensible DRAM simulator","volume":"15","author":"Kim Y.","year":"2015","unstructured":"Y. Kim, W. Yang, and O. Mutlu. 2015. RAMULATOR: A fast and extensible DRAM simulator. IEEE Computer Architecture Letters 15, 1 (2015).","journal-title":"IEEE Computer Architecture Letters"},{"key":"e_1_3_2_49_2","doi-asserted-by":"publisher","DOI":"10.5555\/3041100.3041113"},{"key":"e_1_3_2_50_2","volume-title":"Proceedings of the 7th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)","author":"Hazra T. K.","year":"2016","unstructured":"T. K. Hazra and A. Hore. 2016. A comparative study of Travelling Salesman Problem and solution using different algorithm design techniques. In Proceedings of the 7th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)."},{"key":"e_1_3_2_51_2","volume-title":"Proceedings of the International Electron Devices Meeting (IEDM)","author":"Peng X.","year":"2019","unstructured":"X. Peng et al. 2019. DNN+NeuroSim: An End-to-End benchmarking framework for compute-in-memory accelerators with versatile device technologies. In Proceedings of the International Electron Devices Meeting (IEDM)."},{"key":"e_1_3_2_52_2","first-page":"86","volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Jiang N.","year":"2013","unstructured":"N. Jiang et al. 2013. A detailed and flexible cycle-accurate network-on-chip simulator. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 86\u201396."},{"key":"e_1_3_2_53_2","unstructured":"Intel. 2019. Intel Foveros Interconnect. [Online]."},{"issue":"11","key":"e_1_3_2_54_2","article-title":"Deep learning-based context-aware video content analysis on IoT devices","volume":"11","author":"Gad G.","year":"2022","unstructured":"G. Gad et al. 2022. Deep learning-based context-aware video content analysis on IoT devices. Electronics 11, 11 (2022).","journal-title":"Electronics"},{"key":"e_1_3_2_55_2","article-title":"Multi-neural network based tiled 360\u00b0 video caching with Mobile Edge Computing","author":"Kumar S.","year":"2022","unstructured":"S. Kumar, L. Bhagat, and J. Jin. 2022. Multi-neural network based tiled 360\u00b0 video caching with Mobile Edge Computing. Journal of Network and Computer Applications (2022).","journal-title":"Journal of Network and Computer Applications"},{"key":"e_1_3_2_56_2","first-page":"854","volume-title":"Proceedings of the International Symposium on High Performance Computer Architecture (HPCA)","author":"Gupta U.","year":"2021","unstructured":"U. Gupta et al. 2021. Chasing Carbon: The elusive environmental footprint of computing. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), 854\u2013867"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3608098","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3608098","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:32Z","timestamp":1750178792000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3608098"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,9]]},"references-count":55,"journal-issue":{"issue":"5s","published-print":{"date-parts":[[2023,10,31]]}},"alternative-id":["10.1145\/3608098"],"URL":"https:\/\/doi.org\/10.1145\/3608098","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,9,9]]},"assertion":[{"value":"2023-03-23","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-07-13","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-09-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}