{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T10:07:58Z","timestamp":1781258878945,"version":"3.54.1"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","license":[{"start":{"date-parts":[[2023,9,9]],"date-time":"2023-09-09T00:00:00Z","timestamp":1694217600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2023,10,31]]},"abstract":"<jats:p>Traditional High-Level Synthesis (HLS) provides rapid prototyping of hardware accelerators without coding with Hardware Description Languages (HDLs). However, such an approach does not well support allocating large applications like entire deep neural networks on a single Field Programmable Gate Array (FPGA) device. The approach leads to designs that are inefficient or do not fit into FPGAs due to resource constraints.<\/jats:p>\n          <jats:p>This work proposes to shrink generated designs by coarse-grained resource control based on function sharing in functional Intermediate Representations (IRs). The proposed compiler passes and rewrite system aim at producing valid design points and removing redundant hardware. Such optimizations make fitting entire neural networks on FPGAs feasible and produce competitive performance compared to running specialized kernels for each layer.<\/jats:p>","DOI":"10.1145\/3609109","type":"journal-article","created":{"date-parts":[[2023,9,9]],"date-time":"2023-09-09T13:33:18Z","timestamp":1694266398000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1629-8617","authenticated-orcid":false,"given":"Tzung-Han","family":"Juang","sequence":"first","affiliation":[{"name":"McGill University, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3835-4774","authenticated-orcid":false,"given":"Christof","family":"Schlaak","sequence":"additional","affiliation":[{"name":"University of Edinburgh, United Kingdom"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4811-2469","authenticated-orcid":false,"given":"Christophe","family":"Dubach","sequence":"additional","affiliation":[{"name":"McGill University &amp; Mila, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,9,9]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.3990\/1.9789036538039"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCC47050.2019.9064413"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/872726.806984"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062208"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385983"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8341974"},{"key":"e_1_3_1_10_2","article-title":"AutoPhase: Juggling HLS phase orderings in random forests with deep reinforcement learning","author":"Huang Qijing","year":"2020","unstructured":"Qijing Huang, Ameer Haj-Ali, William Moses, John Xiang, Ion Stoica, Krste Asanovic, and John Wawrzynek. 2020. AutoPhase: Juggling HLS phase orderings in random forests with deep reinforcement learning. arXiv preprint arXiv:2003.00671 (2020).","journal-title":"arXiv preprint arXiv:2003.00671"},{"key":"e_1_3_1_11_2","first-page":"295","volume-title":"2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920)","author":"Jo G.","year":"2020","unstructured":"G. Jo, H. Kim, J. Lee, and J. Lee. 2020. SOFF: An OpenCL high-level synthesis framework for FPGAs. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920). 295\u2013308."},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192379"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/3315454.3329957"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293910"},{"key":"e_1_3_1_15_2","volume-title":"Acceleration of Deep Learning on FPGA","author":"Li Huyuan","year":"2017","unstructured":"Huyuan Li. 2017. Acceleration of Deep Learning on FPGA. Ph.D. Dissertation. University of Windsor (Canada)."},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488795"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2394802"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL57034.2022.00069"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385974"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012172"},{"issue":"5","key":"e_1_3_1_21_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3126566","article-title":"COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators","volume":"16","author":"Piccolboni Luca","year":"2017","unstructured":"Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni. 2017. COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators. 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