{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:08:31Z","timestamp":1750219711737,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":59,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,11,30]],"date-time":"2023-11-30T00:00:00Z","timestamp":1701302400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Intel","award":["NSF 16-606"],"award-info":[{"award-number":["NSF 16-606"]}]},{"DOI":"10.13039\/100000006","name":"Office of Naval Research","doi-asserted-by":"publisher","award":["N00014-18-1-2037"],"award-info":[{"award-number":["N00014-18-1-2037"]}],"id":[{"id":"10.13039\/100000006","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["CHS-1956322 CCF-1764077, CCF-1723773, NSF 16-606"],"award-info":[{"award-number":["CHS-1956322 CCF-1764077, CCF-1723773, NSF 16-606"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,11,30]]},"DOI":"10.1145\/3611643.3616318","type":"proceedings-article","created":{"date-parts":[[2023,11,30]],"date-time":"2023-11-30T23:14:38Z","timestamp":1701386078000},"page":"1101-1113","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Leveraging Hardware Probes and Optimizations for Accelerating Fuzz Testing of Heterogeneous Applications"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-2778-8840","authenticated-orcid":false,"given":"Jiyuan","family":"Wang","sequence":"first","affiliation":[{"name":"University of California at Los Angeles, Los Angeles, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4002-4379","authenticated-orcid":false,"given":"Qian","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of California at Riverside, Riverside, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3275-7791","authenticated-orcid":false,"given":"Hongbo","family":"Rong","sequence":"additional","affiliation":[{"name":"Intel Labs, Santa Clara, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4737-2146","authenticated-orcid":false,"given":"Guoqing Harry","family":"Xu","sequence":"additional","affiliation":[{"name":"University of California at Los Angeles, Los Angeles, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3802-1512","authenticated-orcid":false,"given":"Miryung","family":"Kim","sequence":"additional","affiliation":[{"name":"University of California at Los Angeles, Los Angeles, USA"}]}],"member":"320","published-online":{"date-parts":[[2023,11,30]]},"reference":[{"key":"e_1_3_2_2_1_1","unstructured":"Paul Alcorn. 2022. AMD to Fuse FPGA AI Engines Onto EPYC Processors Arrives in 2023. https:\/\/www.tomshardware.com\/news\/amd-to-fuse-fpga-ai-engines-onto-epyc-processors-arrives-in-2023"},{"key":"e_1_3_2_2_2_1","unstructured":"Amazon.com. 2021. Amazon EC2 F1 Instances: Run Custom FPGAs in the AWS Cloud. https:\/\/aws.amazon.com\/ec2\/instance-types\/f1"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2436256.2436271"},{"key":"e_1_3_2_2_4_1","unstructured":"E Bendersky. 2012. PyCParser C Parser and AST Generator Written in Python."},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3134020"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978428"},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1155\/2010\/540159"},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927496"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554787"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783710"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2011.04.217"},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.44"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2596667"},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00040"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.141"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470747"},{"key":"e_1_3_2_2_18_1","unstructured":"Ian Cutress. 2018. Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA Shipping to Vendors. https:\/\/www.anandtech.com\/show\/12773\/intel-shows-xeon-scalable-gold-6138p-with-integrated-fpga-shipping-to-vendors"},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3460120.3484573"},{"key":"e_1_3_2_2_20_1","volume-title":"Heiko Ei\u00df feldt, and Marc Heuse","author":"Fioraldi Andrea","year":"2020","unstructured":"Andrea Fioraldi, Dominik Maier, Heiko Ei\u00df feldt, and Marc Heuse. 2020. AFL++: Combining Incremental Steps of Fuzzing Research. USENIX Association, USA."},{"key":"e_1_3_2_2_21_1","volume-title":"Allen CH Wu, and Steve YL Lin","author":"Gajski Daniel D","year":"2012","unstructured":"Daniel D Gajski, Nikil D Dutt, Allen CH Wu, and Steve YL Lin. 2012. High\u2014Level Synthesis: Introduction to Chip and System Design. Springer Science & Business Media."},{"key":"e_1_3_2_2_22_1","first-page":"1","article-title":"HDL coding practices to accelerate design performance","volume":"231","author":"Garrault Philippe","year":"2006","unstructured":"Philippe Garrault and Brian Philofsky. 2006. HDL coding practices to accelerate design performance. Xilinx White Paper, 231 (2006), 1\u201322.","journal-title":"Xilinx White Paper"},{"key":"e_1_3_2_2_23_1","doi-asserted-by":"publisher","unstructured":"Licheng Guo Jason Lau Zhenyuan Ruan Peng Wei and Jason Cong. 2019. Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU. In 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 127\u2013135. https:\/\/doi.org\/10.1109\/FCCM.2019.00027 10.1109\/FCCM.2019.00027","DOI":"10.1109\/FCCM.2019.00027"},{"key":"e_1_3_2_2_24_1","unstructured":"Intel. 2021. Dense Linear Algebra. https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/6901f7203b549a651911fec694ffefad82ed0b35\/DirectProgramming\/C%2B%2BSYCL\/DenseLinearAlgebra"},{"key":"e_1_3_2_2_25_1","unstructured":"Intel. 2021. DPC++ Reference. https:\/\/oneapi-src.github.io\/DPCPP_Reference\/"},{"key":"e_1_3_2_2_26_1","unstructured":"Intel. 2022. Devcloud. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/tools\/devcloud\/overview.html"},{"key":"e_1_3_2_2_27_1","unstructured":"Intel. 2022. FPGA Optimization Guide for Intel\u00ae oneAPI Toolkits - Shannonization to Improve FMAX\/II. https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-fpga-optimization-guide\/top\/optimize-your-design\/throughput-1\/single-work-item-kernels\/loops\/shannonization-to-improve-fmax-ii.html"},{"key":"e_1_3_2_2_28_1","unstructured":"Intel. 2022. FPGA Optimization Guide for Intel\u00ae oneAPI Toolkits - Transfer Loop-Carried Dependency to Local Memory. https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-fpga-optimization-guide\/top\/optimize-your-design\/throughput-1\/single-work-item-kernels\/loops\/transfer-loop-carried-dependency-to-local-memory.html"},{"key":"e_1_3_2_2_29_1","unstructured":"Intel. 2022. FPGA Optimization Guide for Intel\u00ae oneAPI Toolkits - Unroll Loops. https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-fpga-optimization-guide\/top\/optimize-your-design\/throughput-1\/single-work-item-kernels\/loops\/unroll-loops.html"},{"key":"e_1_3_2_2_30_1","unstructured":"Intel. 2022. Intel\u00ae Arria\u00ae 10 GX FPGA Overview. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/fpga\/arria\/10\/gx\/products.html"},{"key":"e_1_3_2_2_31_1","unstructured":"Intel. 2022. Intel\u00ae Stratix\u00ae 10 GX FPGA Overview. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/fpga\/stratix\/10.html"},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3243734.3243804"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3375459"},{"key":"e_1_3_2_2_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240842"},{"key":"e_1_3_2_2_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3469660"},{"key":"e_1_3_2_2_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3213846.3213874"},{"key":"e_1_3_2_2_37_1","volume-title":"2016 26th International Conference on Field Programmable Logic and Applications (FPL). 1\u20139.","author":"Li Huimin","year":"2016","unstructured":"Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, and Lingli Wang. 2016. A high performance FPGA-based accelerator for large-scale convolutional neural networks. In 2016 26th International Conference on Field Programmable Logic and Applications (FPL). 1\u20139."},{"key":"e_1_3_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/3236024.3275525"},{"key":"e_1_3_2_2_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021736"},{"key":"e_1_3_2_2_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2019.2946563"},{"key":"e_1_3_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393129"},{"key":"e_1_3_2_2_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2996868"},{"key":"e_1_3_2_2_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2014.25"},{"volume-title":"Data parallel C++: mastering DPC++ for programming of heterogeneous systems using C++ and SYCL","author":"Reinders James","key":"e_1_3_2_2_44_1","unstructured":"James Reinders, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, and Xinmin Tian. 2021. Data parallel C++: mastering DPC++ for programming of heterogeneous systems using C++ and SYCL. Springer Nature."},{"key":"e_1_3_2_2_45_1","volume-title":"SYCL: Single-source C++ accelerator programming. In Parallel Computing: On the Road to Exascale","author":"Reyes Ruyman","year":"2016","unstructured":"Ruyman Reyes and Victor Lom\u00fcller. 2016. SYCL: Single-source C++ accelerator programming. In Parallel Computing: On the Road to Exascale. IOS Press, 673\u2013682."},{"key":"e_1_3_2_2_46_1","volume-title":"Programmatic Control of a Compiler for Generating High-performance Spatial Hardware. CoRR, abs\/1711.07606","author":"Rong Hongbo","year":"2017","unstructured":"Hongbo Rong. 2017. Programmatic Control of a Compiler for Generating High-performance Spatial Hardware. CoRR, abs\/1711.07606 (2017), arxiv:1711.07606. arxiv:1711.07606"},{"key":"e_1_3_2_2_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2011.6157401"},{"key":"e_1_3_2_2_48_1","volume-title":"Silifuzz: Fuzzing cpus by proxy. arXiv preprint arXiv:2110.11519.","author":"Serebryany Kostya","year":"2021","unstructured":"Kostya Serebryany, Maxim Lifantsev, Konstantin Shtoyk, Doug Kwan, and Peter Hochschild. 2021. Silifuzz: Fuzzing cpus by proxy. arXiv preprint arXiv:2110.11519."},{"key":"e_1_3_2_2_49_1","doi-asserted-by":"publisher","DOI":"10.3390\/app9235100"},{"key":"e_1_3_2_2_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/3377811.3380386"},{"key":"e_1_3_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/3377811.3380396"},{"key":"e_1_3_2_2_52_1","unstructured":"Xilinx. 2021. UltraScale Architecture and Product Data Sheet: Overview. https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds890-ultrascale-overview.pdf"},{"key":"e_1_3_2_2_53_1","volume-title":"Proceedings of the 29th USENIX Conference on Security Symposium. 2307\u20132324","author":"Yue Tai","year":"2020","unstructured":"Tai Yue, Pengfei Wang, Yong Tang, Enze Wang, Bo Yu, Kai Lu, and Xu Zhou. 2020. Ecofuzz: Adaptive energy-saving greybox fuzzing as a variant of the adversarial multi-armed bandit. In Proceedings of the 29th USENIX Conference on Security Symposium. 2307\u20132324."},{"key":"e_1_3_2_2_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3024918"},{"key":"e_1_3_2_2_55_1","unstructured":"Micha\u0142 Zalewski. 2021. American Fuzz Loop. http:\/\/lcamtuf.coredump.cx\/afl\/"},{"key":"e_1_3_2_2_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_3_2_2_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/3324884.3416641"},{"key":"e_1_3_2_2_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/3468264.3468610"},{"key":"e_1_3_2_2_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174255"}],"event":{"name":"ESEC\/FSE '23: 31st ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering","sponsor":["SIGSOFT ACM Special Interest Group on Software Engineering"],"location":"San Francisco CA USA","acronym":"ESEC\/FSE '23"},"container-title":["Proceedings of the 31st ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3611643.3616318","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3611643.3616318","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:36:04Z","timestamp":1750178164000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3611643.3616318"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11,30]]},"references-count":59,"alternative-id":["10.1145\/3611643.3616318","10.1145\/3611643"],"URL":"https:\/\/doi.org\/10.1145\/3611643.3616318","relation":{},"subject":[],"published":{"date-parts":[[2023,11,30]]},"assertion":[{"value":"2023-11-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}