{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,14]],"date-time":"2026-07-14T12:35:09Z","timestamp":1784032509099,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":77,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,10,28]],"date-time":"2023-10-28T00:00:00Z","timestamp":1698451200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-sa\/4.0\/"}],"funder":[{"name":"DARPA","award":["N00014-21-1-2960"],"award-info":[{"award-number":["N00014-21-1-2960"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,10,28]]},"DOI":"10.1145\/3613424.3614257","type":"proceedings-article","created":{"date-parts":[[2023,12,8]],"date-time":"2023-12-08T17:22:15Z","timestamp":1702056135000},"page":"153-166","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Accelerating RTL Simulation with Hardware-Software Co-Design"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-7100-0353","authenticated-orcid":false,"given":"Fares","family":"Elsabbagh","sequence":"first","affiliation":[{"name":"MIT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7339-5598","authenticated-orcid":false,"given":"Shabnam","family":"Sheikhha","sequence":"additional","affiliation":[{"name":"MIT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9660-7082","authenticated-orcid":false,"given":"Victor A.","family":"Ying","sequence":"additional","affiliation":[{"name":"MIT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3820-6421","authenticated-orcid":false,"given":"Quan M.","family":"Nguyen","sequence":"additional","affiliation":[{"name":"MIT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3459-5466","authenticated-orcid":false,"given":"Joel S","family":"Emer","sequence":"additional","affiliation":[{"name":"MIT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2453-2904","authenticated-orcid":false,"given":"Daniel","family":"Sanchez","sequence":"additional","affiliation":[{"name":"MIT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,12,8]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378454"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.37"},{"key":"e_1_3_2_1_3_1","volume-title":"Proc. of the 32nd annual Intl. Symp. on Computer Architecture (ISCA-32)","year":"2005","unstructured":"Arvind. 2005 . Passing the token . In Proc. of the 32nd annual Intl. Symp. on Computer Architecture (ISCA-32) . Arvind. 2005. Passing the token. In Proc. of the 32nd annual Intl. Symp. on Computer Architecture (ISCA-32)."},{"key":"e_1_3_2_1_4_1","volume-title":"I-Structures: Data Structures For Parallel Computing. ACM TOPLAS 11, 4","author":"Nikhil S.","year":"1989","unstructured":"Arvind, Rishiyur\u00a0 S. Nikhil , and Keshav\u00a0 K. Pingali . 1989. I-Structures: Data Structures For Parallel Computing. ACM TOPLAS 11, 4 ( 1989 ). Arvind, Rishiyur\u00a0S. Nikhil, and Keshav\u00a0K. Pingali. 1989. I-Structures: Data Structures For Parallel Computing. ACM TOPLAS 11, 4 (1989)."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322234"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.640619"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2997639"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/3437539.3437655"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/285730.285766"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.2000.832227"},{"key":"e_1_3_2_1_11_1","volume-title":"Asynchronous circuits","author":"Brzozowski A","unstructured":"Janusz\u00a0 A Brzozowski and Carl-Johan\u00a0 H Seger . 1995. Asynchronous circuits . Springer . Janusz\u00a0A Brzozowski and Carl-Johan\u00a0H Seger. 1995. Asynchronous circuits. Springer."},{"key":"e_1_3_2_1_12_1","unstructured":"Cadence. 2015. Palladium Z1 enterprise emulation platform. https:\/\/www.cadence.com\/content\/dam\/cadence-www\/global\/en_US\/documents\/tools\/system-design-verification\/palladium-z1-ds.pdf archived at https:\/\/perma.cc\/MD6F-EYGQ.  Cadence. 2015. Palladium Z1 enterprise emulation platform. https:\/\/www.cadence.com\/content\/dam\/cadence-www\/global\/en_US\/documents\/tools\/system-design-verification\/palladium-z1-ds.pdf archived at https:\/\/perma.cc\/MD6F-EYGQ."},{"key":"e_1_3_2_1_13_1","unstructured":"Cadence. 2019. Protium X1 enterprise prototyping platform. https:\/\/www.cadence.com\/en_US\/home\/tools\/system-design-and-verification\/emulation-and-prototyping\/protium.html.  Cadence. 2019. Protium X1 enterprise prototyping platform. https:\/\/www.cadence.com\/en_US\/home\/tools\/system-design-and-verification\/emulation-and-prototyping\/protium.html."},{"key":"e_1_3_2_1_14_1","volume-title":"Asynchronous distributed simulation via a sequence of parallel computations. Commun. ACM 24, 4","author":"Chandy Mani","year":"1981","unstructured":"K.\u00a0 Mani Chandy and Jayadev Misra . 1981. Asynchronous distributed simulation via a sequence of parallel computations. Commun. ACM 24, 4 ( 1981 ). K.\u00a0Mani Chandy and Jayadev Misra. 1981. Asynchronous distributed simulation via a sequence of parallel computations. Commun. ACM 24, 4 (1981)."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/642089.642111"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.13"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/72935.72957"},{"key":"e_1_3_2_1_19_1","volume-title":"Parallel discrete event simulation. Commun. ACM 33, 10","author":"Fujimoto Richard","year":"1990","unstructured":"Richard Fujimoto . 1990. Parallel discrete event simulation. Commun. ACM 33, 10 ( 1990 ). Richard Fujimoto. 1990. Parallel discrete event simulation. Commun. ACM 33, 10 (1990)."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.123382"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310767"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_2_1_23_1","volume-title":"Proc. of the 2018 Intl. Symp. on Physical Design (ISPD).","author":"N.","unstructured":"William\u00a0N. N. Hung and Richard Sun. 2018. Challenges in large FPGA-based logic emulation systems . In Proc. of the 2018 Intl. Symp. on Physical Design (ISPD). William\u00a0N.N. Hung and Richard Sun. 2018. Challenges in large FPGA-based logic emulation systems. In Proc. of the 2018 Intl. Symp. on Physical Design (ISPD)."},{"key":"e_1_3_2_1_24_1","unstructured":"IBS data on IC design costs. 2018. As Chip Design Costs Skyrocket 3nm Process Node Is in Jeopardy. https:\/\/www.extremetech.com\/computing\/272096-3nm-process-node.  IBS data on IC design costs. 2018. As Chip Design Costs Skyrocket 3nm Process Node Is in Jeopardy. https:\/\/www.extremetech.com\/computing\/272096-3nm-process-node."},{"key":"e_1_3_2_1_25_1","volume-title":"Virtual time. ACM TOPLAS 7, 3","author":"Jefferson David","year":"1985","unstructured":"David Jefferson . 1985. Virtual time. ACM TOPLAS 7, 3 ( 1985 ). David Jefferson. 1985. Virtual time. ACM TOPLAS 7, 3 (1985)."},{"key":"e_1_3_2_1_26_1","volume-title":"Proc. of the 11st Symp. on Operating System Principles (SOSP-11)","author":"Jefferson David","year":"1987","unstructured":"David Jefferson , Brian Beckman , Fred Wieland , Leo Blume , Mike DiLoreto , Phil Hontalas , Pierre Laroche , Kathy Sturdevant , Jack Tupman , Van Warren , John Wedel , Herb Younger , and Steve Bellenot . 1987 . Distributed Simulation and the Time Warp Operating System . In Proc. of the 11st Symp. on Operating System Principles (SOSP-11) . David Jefferson, Brian Beckman, Fred Wieland, Leo Blume, Mike DiLoreto, Phil Hontalas, Pierre Laroche, Kathy Sturdevant, Jack Tupman, Van Warren, John Wedel, Herb Younger, and Steve Bellenot. 1987. Distributed Simulation and the Time Warp Operating System. In Proc. of the 11st Symp. on Operating System Principles (SOSP-11)."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830777"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00014"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1137\/S1064827595287997"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1993.410733"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358322"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527415"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380625"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_8"},{"key":"e_1_3_2_1_35_1","volume-title":"Proc. of the 51st Intl. Conf. on Parallel Processing (ICPP-51)","author":"Lin Dian-Lun","year":"2023","unstructured":"Dian-Lun Lin , Haoxing Ren , Yanqing Zhang , Brucek Khailany , and Tsung-Wei Huang . 2023 . From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus . In Proc. of the 51st Intl. Conf. on Parallel Processing (ICPP-51) . Dian-Lun Lin, Haoxing Ren, Yanqing Zhang, Brucek Khailany, and Tsung-Wei Huang. 2023. From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus. In Proc. of the 51st Intl. Conf. on Parallel Processing (ICPP-51)."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_37_1","unstructured":"Mentor\/Siemens. 2017. Veloce Strato. https:\/\/eda.sw.siemens.com\/en-US\/ic\/veloce\/strato-hardware\/.  Mentor\/Siemens. 2017. Veloce Strato. https:\/\/eda.sw.siemens.com\/en-US\/ic\/veloce\/strato-hardware\/."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"e_1_3_2_1_39_1","unstructured":"Nangate Inc.2008. The NanGate 45nm Open Cell Library. http:\/\/www.nangate.com\/?page_id=2325.  Nangate Inc.2008. The NanGate 45nm Open Cell Library. http:\/\/www.nangate.com\/?page_id=2325."},{"key":"e_1_3_2_1_40_1","article-title":"Executing a program on the MIT tagged-token dataflow architecture","volume":"39","author":"Nikhil S.","year":"1990","unstructured":"Rishiyur\u00a0 S. Nikhil and Arvind. 1990 . Executing a program on the MIT tagged-token dataflow architecture . IEEE Trans. on Computers 39 , 3 (1990). Rishiyur\u00a0S. Nikhil and Arvind. 1990. Executing a program on the MIT tagged-token dataflow architecture. IEEE Trans. on Computers 39, 3 (1990).","journal-title":"IEEE Trans. on Computers"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080255"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750380"},{"key":"e_1_3_2_1_43_1","volume-title":"Controlling Program Execution through Binary Instrumentation. SIGARCH Computer Architecture News","author":"Pan Heidi","year":"2005","unstructured":"Heidi Pan , Krste Asanovi\u0107 , Robert Cohn , and Chi-Keung Luk . 2005. Controlling Program Execution through Binary Instrumentation. SIGARCH Computer Architecture News ( 2005 ). Heidi Pan, Krste Asanovi\u0107, Robert Cohn, and Chi-Keung Luk. 2005. Controlling Program Execution through Binary Instrumentation. SIGARCH Computer Architecture News (2005)."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/18927.18916"},{"key":"e_1_3_2_1_45_1","volume-title":"Proc. of the 19th Design Automation Conf. (DAC-19)","author":"Pfister F","year":"1982","unstructured":"Gregory\u00a0 F Pfister . 1982 . The Yorktown simulation engine: Introduction . In Proc. of the 19th Design Automation Conf. (DAC-19) . Gregory\u00a0F Pfister. 1982. The Yorktown simulation engine: Introduction. In Proc. of the 19th Design Automation Conf. (DAC-19)."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446720"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088178"},{"key":"e_1_3_2_1_48_1","unstructured":"Lauro Rizzatti. 2015. Hardware emulation: Three decades of evolution. Part I. https:\/\/s3.amazonaws.com\/verificationhorizons.verificationacademy.com\/volume-11_issue-1\/articles\/stream\/hardware-emulation-three-decades-of-evolution_vh-v11-i1.pdf archived at https:\/\/perma.cc\/F3DU-U6ZK. Verification Horizons 11 1 (2015) 26\u201327.  Lauro Rizzatti. 2015. Hardware emulation: Three decades of evolution. Part I. https:\/\/s3.amazonaws.com\/verificationhorizons.verificationacademy.com\/volume-11_issue-1\/articles\/stream\/hardware-emulation-three-decades-of-evolution_vh-v11-i1.pdf archived at https:\/\/perma.cc\/F3DU-U6ZK. Verification Horizons 11 1 (2015) 26\u201327."},{"key":"e_1_3_2_1_49_1","unstructured":"Lauro Rizzatti. 2015. Hardware emulation: Three decades of evolution. Part II. https:\/\/s3.amazonaws.com\/verificationhorizons.verificationacademy.com\/volume-11_issue-2\/articles\/stream\/hardware-emulation-three-decades-of-evolution-part-II_vh-v11-i2.pdf archived at https:\/\/perma.cc\/XB4N-C7MS. Verification Horizons 11 2 (2015) 40\u201342.  Lauro Rizzatti. 2015. Hardware emulation: Three decades of evolution. Part II. https:\/\/s3.amazonaws.com\/verificationhorizons.verificationacademy.com\/volume-11_issue-2\/articles\/stream\/hardware-emulation-three-decades-of-evolution-part-II_vh-v11-i2.pdf archived at https:\/\/perma.cc\/XB4N-C7MS. Verification Horizons 11 2 (2015) 40\u201342."},{"key":"e_1_3_2_1_50_1","unstructured":"Lauro Rizzatti. 2015. Hardware emulation: Three decades of evolution. Part III. https:\/\/s3.amazonaws.com\/verificationhorizons.verificationacademy.com\/volume-11_issue-3\/articles\/stream\/hardware-emulation-three-decades-of-evolution-part-iii_vh-v11-i3.pdf archived at https:\/\/perma.cc\/BK4D-NAJX. Verification Horizons 11 3 (2015) 15\u201318.  Lauro Rizzatti. 2015. Hardware emulation: Three decades of evolution. Part III. https:\/\/s3.amazonaws.com\/verificationhorizons.verificationacademy.com\/volume-11_issue-3\/articles\/stream\/hardware-emulation-three-decades-of-evolution-part-iii_vh-v11-i3.pdf archived at https:\/\/perma.cc\/BK4D-NAJX. Verification Horizons 11 3 (2015) 15\u201318."},{"key":"e_1_3_2_1_51_1","volume-title":"Alder Lake Architecture. In IEEE Hot Chips 33 Symposium (HotChips-33)","author":"Rotem Efraim","year":"2021","unstructured":"Efraim Rotem , Yuli Mandelblat , Vadim Basin , Eli Weissmann , Arik Gihon , Rajshree Chabukswar , Russ Fenger , and Monica Gupta . 2021 . Alder Lake Architecture. In IEEE Hot Chips 33 Symposium (HotChips-33) . Efraim Rotem, Yuli Mandelblat, Vadim Basin, Eli Weissmann, Arik Gihon, Rajshree Chabukswar, Russ Fenger, and Monica Gupta. 2021. Alder Lake Architecture. In IEEE Hot Chips 33 Symposium (HotChips-33)."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480070"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527393"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.94"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_3_2_1_56_1","unstructured":"Wilson Snyder. 2003. Verilator. https:\/\/www.veripool.org\/verilator\/.  Wilson Snyder. 2003. Verilator. https:\/\/www.veripool.org\/verilator\/."},{"key":"e_1_3_2_1_57_1","volume-title":"The Open Source Digital Design Conference (ORConf).","author":"Snyder Wilson","year":"2018","unstructured":"Wilson Snyder . 2018 . Verilator 4.0: Open Source Simulation Goes Multithreaded . In The Open Source Digital Design Conference (ORConf). Wilson Snyder. 2018. Verilator 4.0: Open Source Simulation Goes Multithreaded. In The Open Source Digital Design Conference (ORConf)."},{"key":"e_1_3_2_1_58_1","volume-title":"Accelerated. In 2nd Workshop on Open-Source Design Automation (OSDA).","author":"Snyder Wilson","year":"2020","unstructured":"Wilson Snyder . 2020 . Verilator , Accelerated. In 2nd Workshop on Open-Source Design Automation (OSDA). Wilson Snyder. 2020. Verilator, Accelerated. In 2nd Workshop on Open-Source Design Automation (OSDA)."},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224451"},{"key":"e_1_3_2_1_60_1","unstructured":"SpinalHDL. 2018. A FPGA friendly 32 bit RISC-V CPU implementation. https:\/\/github.com\/SpinalHDL\/VexRiscv.  SpinalHDL. 2018. A FPGA friendly 32 bit RISC-V CPU implementation. https:\/\/github.com\/SpinalHDL\/VexRiscv."},{"key":"e_1_3_2_1_61_1","volume-title":"Proc. of the 4th IEEE intl. symp. on High Performance Computer Architecture (HPCA-4).","author":"J.","unstructured":"J. \u00a0Gregory Steffan and Todd\u00a0C. Mowry. 1998. The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization . In Proc. of the 4th IEEE intl. symp. on High Performance Computer Architecture (HPCA-4). J.\u00a0Gregory Steffan and Todd\u00a0C. Mowry. 1998. The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization. In Proc. of the 4th IEEE intl. symp. on High Performance Computer Architecture (HPCA-4)."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233307.1233308"},{"key":"e_1_3_2_1_63_1","unstructured":"Synopsys Inc.2018. ZeBu Server 4. https:\/\/www.synopsys.com\/verification\/emulation\/zebu-server.html.  Synopsys Inc.2018. ZeBu Server 4. https:\/\/www.synopsys.com\/verification\/emulation\/zebu-server.html."},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694362"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837390"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815999"},{"key":"e_1_3_2_1_67_1","unstructured":"The Chronos FPGA Framework to accelerate ordered applications. 2020. https:\/\/github.com\/SwarmArch\/chronos\/.  The Chronos FPGA Framework to accelerate ordered applications. 2020. https:\/\/github.com\/SwarmArch\/chronos\/."},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480128"},{"key":"e_1_3_2_1_69_1","volume-title":"An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of research and Development 11, 1","author":"Tomasulo M","year":"1967","unstructured":"Robert\u00a0 M Tomasulo . 1967. An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of research and Development 11, 1 ( 1967 ). Robert\u00a0M Tomasulo. 1967. An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of research and Development 11, 1 (1967)."},{"key":"e_1_3_2_1_70_1","unstructured":"Ray Turner. 2004. A primer on processor-based emulation. EETimes https:\/\/www.eetimes.com\/a-primer-on-processor-based-emulation\/.  Ray Turner. 2004. A primer on processor-based emulation. EETimes https:\/\/www.eetimes.com\/a-primer-on-processor-based-emulation\/."},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582034"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"e_1_3_2_1_73_1","unstructured":"Claire Wolf. 2014. Yosys Open SYnthesis Suite. http:\/\/www.clifford.at\/yosys\/.  Claire Wolf. 2014. Yosys Open SYnthesis Suite. http:\/\/www.clifford.at\/yosys\/."},{"key":"e_1_3_2_1_74_1","unstructured":"Xilinx. 2019. Alveo U250 Data Center Accelerator Card. https:\/\/www.xilinx.com\/products\/boards-and-kits\/alveo\/u250.html.  Xilinx. 2019. Alveo U250 Data Center Accelerator Card. https:\/\/www.xilinx.com\/products\/boards-and-kits\/alveo\/u250.html."},{"key":"e_1_3_2_1_75_1","volume-title":"on Parallel and Distributed Systems","author":"Yazdanpanah Fahimeh","year":"2013","unstructured":"Fahimeh Yazdanpanah , Carlos Alvarez-Martinez , Daniel Jimenez-Gonzalez , and Yoav Etsion . 2013. Hybrid Dataflow\/ Von-Neumann Architectures . IEEE Trans . on Parallel and Distributed Systems ( 2013 ). Fahimeh Yazdanpanah, Carlos Alvarez-Martinez, Daniel Jimenez-Gonzalez, and Yoav Etsion. 2013. Hybrid Dataflow\/Von-Neumann Architectures. IEEE Trans. on Parallel and Distributed Systems (2013)."},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00024"},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2012.7476498"}],"event":{"name":"MICRO '23: 56th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Toronto ON Canada","acronym":"MICRO '23","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["56th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3613424.3614257","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3613424.3614257","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3613424.3614257","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:21Z","timestamp":1750178781000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3613424.3614257"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,28]]},"references-count":77,"alternative-id":["10.1145\/3613424.3614257","10.1145\/3613424"],"URL":"https:\/\/doi.org\/10.1145\/3613424.3614257","relation":{},"subject":[],"published":{"date-parts":[[2023,10,28]]},"assertion":[{"value":"2023-12-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}