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A Multi-Neural Network Acceleration Architecture . In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 940\u2013953 . Eunjin Baek, Dongup Kwon, and Jangwoo Kim. 2020. A Multi-Neural Network Acceleration Architecture. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 940\u2013953."},{"key":"e_1_3_2_1_4_1","volume-title":"Software-Defined Vector Processing on Manycore Fabrics. In MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture. 392\u2013406","author":"Bedoukian Philip","year":"2021","unstructured":"Philip Bedoukian , Neil Adit , Edwin Peguero , and Adrian Sampson . 2021 . Software-Defined Vector Processing on Manycore Fabrics. In MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture. 392\u2013406 . Philip Bedoukian, Neil Adit, Edwin Peguero, and Adrian Sampson. 2021. Software-Defined Vector Processing on Manycore Fabrics. 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Empirical Evaluation of Gated Recurrent Neural Networks on Sequence Modeling. arXiv preprint arXiv:1412.3555 (2014)."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840883"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.022071133"},{"key":"e_1_3_2_1_15_1","volume-title":"Chip. In 2021 IEEE Hot Chips 33 Symposium (HCS). IEEE, 1\u201323","author":"Ditzel Dave","year":"2021","unstructured":"Dave Ditzel , Roger Espasa , Nivard Aymerich , Allen Baum , Tom Berg , Jim Burr , Eric Hao , Jayesh Iyer , Miquel Izquierdo , Shankar Jayaratnam , 2021 . Accelerating ML Recommendation with over a Thousand RISC-V\/Tensor Processors on Esperanto\u2019s ET-SoC-1 Chip. In 2021 IEEE Hot Chips 33 Symposium (HCS). IEEE, 1\u201323 . Dave Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, 2021. 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In 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). IEEE, 383\u2013396."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00012"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322257"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037702"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304014"},{"key":"e_1_3_2_1_22_1","volume-title":"AI and Memory Wall. RiseLab Medium Post","author":"Gholami Amir","year":"2021","unstructured":"Amir Gholami , Zhewei Yao , Sehoon Kim , Michael\u00a0 W Mahoney , and Kurt Keutzer . 2021. AI and Memory Wall. RiseLab Medium Post ( 2021 ). Amir Gholami, Zhewei Yao, Sehoon Kim, Michael\u00a0W Mahoney, and Kurt Keutzer. 2021. AI and Memory Wall. RiseLab Medium Post (2021)."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2014.81"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1002\/rob.21918"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.8.1735"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00286"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"e_1_3_2_1_31_1","volume-title":"Energy-efficient and High Throughput Sparse Distributed Memory Architecture. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS). 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HT Kung Bradley McDanel Sai\u00a0Qian Zhang Xin Dong and Chih\u00a0Chiang Chen. 2019. Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays. In 2019 IEEE 30th International Conference on Application-specific Systems Architectures and Processors (ASAP) Vol.\u00a02160. IEEE 42\u201350.","DOI":"10.1109\/ASAP.2019.00-31"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.2973991"},{"key":"e_1_3_2_1_35_1","volume-title":"FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 553\u2013564","author":"Lu Wenyan","year":"2017","unstructured":"Wenyan Lu , Guihai Yan , Jiajun Li , Shijun Gong , Yinhe Han , and Xiaowei Li . 2017 . FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 553\u2013564 . Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, and Xiaowei Li. 2017. FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 553\u2013564."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MITS.2019.2907630"},{"key":"e_1_3_2_1_37_1","volume-title":"d.]. \"Nvidia System Management Interface.\". https:\/\/developer.nvidia.com\/nvidia-system-management-interface, accessed","author":"Nvidia Corporation","year":"2023","unstructured":"Nvidia Corporation . [n. d.]. \"Nvidia System Management Interface.\". https:\/\/developer.nvidia.com\/nvidia-system-management-interface, accessed 20 April 2023 .. Nvidia Corporation. [n. d.]. \"Nvidia System Management Interface.\". https:\/\/developer.nvidia.com\/nvidia-system-management-interface, accessed 20 April 2023.."},{"key":"e_1_3_2_1_38_1","volume-title":"Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip. arXiv preprint arXiv:1610.01832","author":"Olofsson Andreas","year":"2016","unstructured":"Andreas Olofsson . 2016. Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip. arXiv preprint arXiv:1610.01832 ( 2016 ). Andreas Olofsson. 2016. Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip. arXiv preprint arXiv:1610.01832 (2016)."},{"key":"e_1_3_2_1_39_1","volume-title":"2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1\u20135.","author":"Patsidis Kariofyllis","year":"2020","unstructured":"Kariofyllis Patsidis , Chrysostomos Nicopoulos , Georgios\u00a0Ch Sirakoulis , and Giorgos Dimitrakopoulos . 2020 . RISC-V2: A Scalable RISC-V Vector Processor . In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1\u20135. Kariofyllis Patsidis, Chrysostomos Nicopoulos, Georgios\u00a0Ch Sirakoulis, and Giorgos Dimitrakopoulos. 2020. RISC-V2: A Scalable RISC-V Vector Processor. In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 1\u20135."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.91"},{"key":"e_1_3_2_1_41_1","volume-title":"Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks. Advances in Neural Information Processing Systems 28","author":"Ren Shaoqing","year":"2015","unstructured":"Shaoqing Ren , Kaiming He , Ross Girshick , and Jian Sun . 2015. Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks. Advances in Neural Information Processing Systems 28 ( 2015 ). Shaoqing Ren, Kaiming He, Ross Girshick, and Jian Sun. 2015. Faster R-CNN: Towards Real-Time Object Detection with Region Proposal Networks. Advances in Neural Information Processing Systems 28 (2015)."},{"key":"e_1_3_2_1_42_1","volume-title":"Glow: Graph Lowering Compiler Techniques for Neural Networks. arXiv preprint arXiv:1805.00907","author":"Rotem Nadav","year":"2018","unstructured":"Nadav Rotem , Jordan Fix , Saleem Abdulrasool , Garret Catron , Summer Deng , Roman Dzhabarov , Nick Gibson , James Hegeman , Meghan Lele , Roman Levenstein , 2018 . Glow: Graph Lowering Compiler Techniques for Neural Networks. arXiv preprint arXiv:1805.00907 (2018). Nadav Rotem, Jordan Fix, Saleem Abdulrasool, Garret Catron, Summer Deng, Roman Dzhabarov, Nick Gibson, James Hegeman, Meghan Lele, Roman Levenstein, 2018. Glow: Graph Lowering Compiler Techniques for Neural Networks. arXiv preprint arXiv:1805.00907 (2018)."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2972528"},{"key":"e_1_3_2_1_44_1","volume-title":"Very Deep Convolutional Networks for Large-Scale Image Recognition. arXiv preprint arXiv:1409.1556","author":"Simonyan Karen","year":"2014","unstructured":"Karen Simonyan and Andrew Zisserman . 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. arXiv preprint arXiv:1409.1556 ( 2014 ). Karen Simonyan and Andrew Zisserman. 2014. Very Deep Convolutional Networks for Large-Scale Image Recognition. arXiv preprint arXiv:1409.1556 (2014)."},{"key":"e_1_3_2_1_45_1","volume-title":"DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling. In 2012 IEEE\/ACM Sixth International Symposium on Networks-on-Chip. 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Synopsys Inc.[n. d.]. \"Synopsys Memory Compilers.\". https:\/\/www.synopsys.com\/dw\/ipdir.php?ds=dwc_sram_memory _compilers accessed 20 April 2023.."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.308"},{"key":"e_1_3_2_1_49_1","volume-title":"Advances in Neural Information Processing Systems 30","author":"Vaswani Ashish","year":"2017","unstructured":"Ashish Vaswani , Noam Shazeer , Niki Parmar , Jakob Uszkoreit , Llion Jones , Aidan\u00a0 N Gomez , \u0141ukasz Kaiser , and Illia Polosukhin . 2017. Attention Is All You Need. Advances in Neural Information Processing Systems 30 ( 2017 ). Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan\u00a0N Gomez, \u0141ukasz Kaiser, and Illia Polosukhin. 2017. Attention Is All You Need. Advances in Neural Information Processing Systems 30 (2017)."},{"key":"e_1_3_2_1_50_1","volume-title":"RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 153\u2013166","author":"Venkataramani Swagath","year":"2021","unstructured":"Swagath Venkataramani , Vijayalakshmi Srinivasan , Wei Wang , Sanchari Sen , Jintao Zhang , Ankur Agrawal , Monodeep Kar , Shubham Jain , Alberto Mannari , Hoang Tran , 2021 . RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 153\u2013166 . Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, 2021. RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. 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