{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T05:01:23Z","timestamp":1764306083221,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,10,18]],"date-time":"2023-10-18T00:00:00Z","timestamp":1697587200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,10,18]]},"DOI":"10.1145\/3623507.3623553","type":"proceedings-article","created":{"date-parts":[[2023,10,19]],"date-time":"2023-10-19T13:39:45Z","timestamp":1697722785000},"page":"73-82","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Gigue: A JIT Code Binary Generator for Hardware Testing"],"prefix":"10.1145","author":[{"given":"Quentin","family":"Ducasse","sequence":"first","affiliation":[{"name":"ENSTA Bretagne, Brest, France"}]},{"given":"Pascal","family":"Cotret","sequence":"additional","affiliation":[{"name":"ENSTA Bretagne, Brest, France"}]},{"given":"Lo\u00efc","family":"Lagadec","sequence":"additional","affiliation":[{"name":"ENSTA Bretagne, Brest, France"}]}],"member":"320","published-online":{"date-parts":[[2023,10,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"CHIPS Alliance. 2023. Chisel\/FIRRTL Hardware Compiler Framework. https:\/\/www.chisel-lang.org\/ \t\t\t\t  CHIPS Alliance. 2023. Chisel\/FIRRTL Hardware Compiler Framework. https:\/\/www.chisel-lang.org\/"},{"key":"e_1_3_2_1_2_1","unstructured":"Krste Asanovic Rimas Avizienis Jonathan Bachrach Scott Beamer David Biancolin Christopher Celio Henry Cook Daniel Dabbelt John Hauser and Adam Izraelevitz. 2016. The Rocket chip generator. \t\t\t\t  Krste Asanovic Rimas Avizienis Jonathan Bachrach Scott Beamer David Biancolin Christopher Celio Henry Cook Daniel Dabbelt John Hauser and Adam Izraelevitz. 2016. The Rocket chip generator."},{"key":"e_1_3_2_1_3_1","volume-title":"Proceedings of the USENIX Annual Conference (ATEC\u201905)","author":"Bellard Fabrice","year":"2005","unstructured":"Fabrice Bellard . 2005 . QEMU, a Fast and Portable Dynamic Translator . In Proceedings of the USENIX Annual Conference (ATEC\u201905) . 41\u201346. https:\/\/www.usenix.org\/legacy\/events\/usenix05\/tech\/freenix\/bellard.html Fabrice Bellard. 2005. QEMU, a Fast and Portable Dynamic Translator. In Proceedings of the USENIX Annual Conference (ATEC\u201905). 41\u201346. https:\/\/www.usenix.org\/legacy\/events\/usenix05\/tech\/freenix\/bellard.html"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.23919\/date.2019.8714980"},{"key":"e_1_3_2_1_5_1","volume-title":"Gigue: Benchmark Setup and Code Generator for JIT code on RISC-V. https:\/\/github.com\/qducasse\/gigue","author":"Ducasse Quentin","year":"2023","unstructured":"Quentin Ducasse . 2023 . Gigue: Benchmark Setup and Code Generator for JIT code on RISC-V. https:\/\/github.com\/qducasse\/gigue Quentin Ducasse. 2023. Gigue: Benchmark Setup and Code Generator for JIT code on RISC-V. https:\/\/github.com\/qducasse\/gigue"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3546918.3546924"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1098\/rsta.2019.0155"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/bfb0057013"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/263698.263754"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415727"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3092627.3092629"},{"key":"e_1_3_2_1_12_1","volume-title":"Proceedings of the 5th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages (VMIL\u201911)","author":"Miranda Eliot","year":"2011","unstructured":"Eliot Miranda . 2011 . The Cog Smalltalk virtual machine . In Proceedings of the 5th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages (VMIL\u201911) . Eliot Miranda. 2011. The Cog Smalltalk virtual machine. In Proceedings of the 5th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages (VMIL\u201911)."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3475738.3480715"},{"key":"e_1_3_2_1_14_1","volume-title":"Capstone: Next-gen disassembly framework. https:\/\/www.capstone-engine.org\/BHUSA2014-capstone.pdf Black Hat USA","author":"Quynh Nguyen Anh","year":"2014","unstructured":"Nguyen Anh Quynh . 2014 . Capstone: Next-gen disassembly framework. https:\/\/www.capstone-engine.org\/BHUSA2014-capstone.pdf Black Hat USA Nguyen Anh Quynh. 2014. Capstone: Next-gen disassembly framework. https:\/\/www.capstone-engine.org\/BHUSA2014-capstone.pdf Black Hat USA"},{"key":"e_1_3_2_1_15_1","volume-title":"Unicorn: Next generation CPU emulator framework. https:\/\/www.unicorn-engine.org\/BHUSA2015-unicorn.pdf Black Hat USA","author":"Quynh Nguyen Anh","year":"2015","unstructured":"Nguyen Anh Quynh and Dang Hoang Vu . 2015 . Unicorn: Next generation CPU emulator framework. https:\/\/www.unicorn-engine.org\/BHUSA2015-unicorn.pdf Black Hat USA Nguyen Anh Quynh and Dang Hoang Vu. 2015. Unicorn: Next generation CPU emulator framework. https:\/\/www.unicorn-engine.org\/BHUSA2015-unicorn.pdf Black Hat USA"},{"key":"e_1_3_2_1_16_1","unstructured":"riscv-software src. 2023. riscv-tests. https:\/\/github.com\/riscv-software-src\/riscv-tests \t\t\t\t  riscv-software src. 2023. riscv-tests. https:\/\/github.com\/riscv-software-src\/riscv-tests"},{"key":"e_1_3_2_1_17_1","volume-title":"Shweta Shinde, Srdjan Capkun, and Ronald Perez.","author":"Schneider Moritz","year":"2022","unstructured":"Moritz Schneider , Ramya Jayaram Masti , Shweta Shinde, Srdjan Capkun, and Ronald Perez. 2022 . SoK: hardware-supported trusted execution environments. Computing Research Repository (CoRR) , https:\/\/doi.org\/10.48550\/arXiv.2205.12742 10.48550\/arXiv.2205.12742 Moritz Schneider, Ramya Jayaram Masti, Shweta Shinde, Srdjan Capkun, and Ronald Perez. 2022. SoK: hardware-supported trusted execution environments. Computing Research Repository (CoRR), https:\/\/doi.org\/10.48550\/arXiv.2205.12742"},{"key":"e_1_3_2_1_18_1","unstructured":"Veripool. 2023. Verilator. https:\/\/www.veripool.org\/verilator\/ \t\t\t\t  Veripool. 2023. Verilator. https:\/\/www.veripool.org\/verilator\/"},{"key":"e_1_3_2_1_19_1","unstructured":"Andrew Waterman Krste Asanovic and SiFive Inc. 2019. The RISC-V instruction set manual Volume I: unprivileged ISA. https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/tag\/Ratified-IMAFDQC \t\t\t\t  Andrew Waterman Krste Asanovic and SiFive Inc. 2019. The RISC-V instruction set manual Volume I: unprivileged ISA. https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/tag\/Ratified-IMAFDQC"},{"key":"e_1_3_2_1_20_1","unstructured":"Andrew Waterman Krste Asanovic and SiFive Inc. 2021. The RISC-V Instruction Set Manual Volume II: Privileged Architecture. https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/tag\/Priv-v1.12 \t\t\t\t  Andrew Waterman Krste Asanovic and SiFive Inc. 2021. The RISC-V Instruction Set Manual Volume II: Privileged Architecture. https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/tag\/Priv-v1.12"}],"event":{"name":"VMIL '23: 15th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGAda ACM Special Interest Group on Ada Programming Language"],"location":"Cascais Portugal","acronym":"VMIL '23"},"container-title":["Proceedings of the 15th ACM SIGPLAN International Workshop on Virtual Machines and Intermediate Languages"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3623507.3623553","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3623507.3623553","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:51:01Z","timestamp":1750287061000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3623507.3623553"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,18]]},"references-count":20,"alternative-id":["10.1145\/3623507.3623553","10.1145\/3623507"],"URL":"https:\/\/doi.org\/10.1145\/3623507.3623553","relation":{},"subject":[],"published":{"date-parts":[[2023,10,18]]},"assertion":[{"value":"2023-10-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}