{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:35:18Z","timestamp":1773246918423,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":61,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Science Foundation of China","award":["T2325001,T2293700,T2293701"],"award-info":[{"award-number":["T2325001,T2293700,T2293701"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,4]]},"DOI":"10.1145\/3626202.3637561","type":"proceedings-article","created":{"date-parts":[[2024,4,2]],"date-time":"2024-04-02T18:04:51Z","timestamp":1712081091000},"page":"211-222","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3636-3685","authenticated-orcid":false,"given":"Youwei","family":"Xiao","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7276-2317","authenticated-orcid":false,"given":"Zizhang","family":"Luo","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7635-3425","authenticated-orcid":false,"given":"Kexing","family":"Zhou","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9076-7998","authenticated-orcid":false,"given":"Yun","family":"Liang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University &amp; Advanced Innovation Center for Integrated Circuits, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2024,4,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070953"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2010.21"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218553"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385965"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240850"},{"key":"e_1_3_2_1_8_1","unstructured":"ChipFlow. [n. d.]. Amaranth HDL. https:\/\/github.com\/amaranth-lang\/amaranth"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3110268"},{"key":"e_1_3_2_1_10_1","volume-title":"Retrieved","author":"Community CIRCT","year":"2022","unstructured":"CIRCT Community. 2022. CIRCT: Circuit IR Compilers and Tools. Retrieved October 31, 2022 from https:\/\/github.com\/llvm\/circt"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240838"},{"key":"e_1_3_2_1_12_1","unstructured":"Jan Decaluwe. [n. d.]. MyHDL. https:\/\/www.myhdl.org\/"},{"key":"e_1_3_2_1_13_1","unstructured":"John Demme. 2021. Elastic Silicon Interconnects: Abstracting Communication in Accelerator Design. arXiv:2111.06584 [cs.AR]"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502368"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385983"},{"key":"e_1_3_2_1_16_1","volume-title":"NICA: An Infrastructure for Inline Acceleration of Network Applications. In 2019 USENIX Annual Technical Conference (USENIX ATC 19)","author":"Eran Haggai","year":"2019","unstructured":"Haggai Eran, Lior Zeno, Maroun Tork, Gabi Malka, and Mark Silberstein. 2019. NICA: An Infrastructure for Inline Acceleration of Network Applications. In 2019 USENIX Annual Technical Conference (USENIX ATC 19). USENIX Association, Renton, WA, 345--362. https:\/\/www.usenix.org\/conference\/atc19\/presentation\/ eran"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586110"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586216"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3575693.3575701"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2601097.2601174"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897824.2925892"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643582"},{"key":"e_1_3_2_1_23_1","unstructured":"Intel. [n. d.]. Intel\u00ae High Level Synthesis Compiler. https:\/\/www.intel.com\/ content\/www\/us\/en\/software\/programmable\/quartus-prime\/hls-compiler.html"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586329"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530411"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00034"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"e_1_3_2_1_29_1","unstructured":"Julian Kemmerer. [n. d.]. PipelineC. https:\/\/github.com\/JulianKemmerer\/ PipelineC"},{"key":"e_1_3_2_1_30_1","volume-title":"The Rust Programming Language","author":"Klabnik Steve","unstructured":"Steve Klabnik and Carol Nichols. 2018. The Rust Programming Language. No Starch Press, USA."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192379"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293910"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415644"},{"key":"e_1_3_2_1_34_1","volume-title":"MLIR: A Compiler Infrastructure for the End of Moore's Law. ArXiv abs\/2002.11054","author":"Lattner Chris","year":"2020","unstructured":"Chris Lattner, Jacques A. Pienaar, Mehdi Amini, Uday Bondhugula, River Riddle, Albert Cohen, Tatiana Shpeisman, Andy Davis, Nicolas Vasilache, and Oleksandr Zinenko. 2020. MLIR: A Compiler Infrastructure for the End of Moore's Law. ArXiv abs\/2002.11054 (2020)."},{"key":"e_1_3_2_1_35_1","unstructured":"Sylvain Lefebvre. [n. d.]. Silice. https:\/\/github.com\/sylefeb\/Silice"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.50"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247743"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385974"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3591234"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446712"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2004.1459818"},{"key":"e_1_3_2_1_42_1","unstructured":"Open-source [n. d.]. SpinalHDL. https:\/\/github.com\/SpinalHDL\/SpinalHDL"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/3107953"},{"key":"e_1_3_2_1_44_1","volume-title":"SSA-Based Compiler Design","author":"Rastello Fabrice","unstructured":"Fabrice Rastello. 2016. SSA-Based Compiler Design (1st ed.). Springer Publishing Company, Incorporated.","edition":"1"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783720"},{"key":"e_1_3_2_1_46_1","volume-title":"Spade: An Expression-Based HDL With Pipelines. arXiv:2304.03079 [cs.AR]","author":"Skarman Frans","year":"2023","unstructured":"Frans Skarman and Oscar Gustafsson. 2023. Spade: An Expression-Based HDL With Pipelines. arXiv:2304.03079 [cs.AR]"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378495"},{"key":"e_1_3_2_1_48_1","unstructured":"Veripool. [n. d.]. Verilator. https:\/\/veripool.org\/verilator\/"},{"key":"e_1_3_2_1_49_1","volume-title":"Proceedings of the 16th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages","author":"Wadler P.","unstructured":"P. Wadler and S. Blott. 1989. How to Make Ad-Hoc Polymorphism Less Ad Hoc. In Proceedings of the 16th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (Austin, Texas, USA) (POPL '89). Association for Computing Machinery, New York, NY, USA, 60--76. https:\/\/doi.org\/10.1145\/ 75277.75283"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/3050220.3050234"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439292"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062251"},{"key":"e_1_3_2_1_53_1","volume-title":"Retrieved","author":"DSL","year":"2023","unstructured":"xDSL project. 2023. xDSL: A Python-native SSA Compiler Framework. Retrieved October 12, 2023 from https:\/\/github.com\/xdslproject\/xdsl"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502369"},{"key":"e_1_3_2_1_55_1","unstructured":"Xilinx Inc. 2023. Vitis High-Level Synthesis User Guide (UG1399). https:\/\/docs. xilinx.com\/r\/2022.1-English\/ug1399-vitis-hls\/Getting-Started-with-Vitis-HLS"},{"key":"e_1_3_2_1_56_1","unstructured":"Xilinx Inc. 2023. Vivado ML. https:\/\/www.xilinx.com\/products\/design-tools\/ vivado.html"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549370"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530631"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/3477002"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","unstructured":"Zhiru Zhang Yiping Fan Wei Jiang Guoling Han Changqi Yang and Jason Cong. 2008. AutoPilot: A platform-based ESL synthesis system. 99--112. https: \/\/doi.org\/10.1007\/978--1--4020--8588--8","DOI":"10.1007\/978--1--4020--8588--8"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/3613424.3614301"}],"event":{"name":"FPGA '24: The 2024 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey CA USA","acronym":"FPGA '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2024 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3626202.3637561","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3626202.3637561","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T22:04:33Z","timestamp":1755900273000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3626202.3637561"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4]]},"references-count":61,"alternative-id":["10.1145\/3626202.3637561","10.1145\/3626202"],"URL":"https:\/\/doi.org\/10.1145\/3626202.3637561","relation":{},"subject":[],"published":{"date-parts":[[2024,4]]},"assertion":[{"value":"2024-04-02","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}