{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:16:59Z","timestamp":1781194619779,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,4]]},"DOI":"10.1145\/3626202.3637571","type":"proceedings-article","created":{"date-parts":[[2024,4,2]],"date-time":"2024-04-02T18:04:51Z","timestamp":1712081091000},"page":"22-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7580-0668","authenticated-orcid":false,"given":"Shaoxian","family":"Xu","sequence":"first","affiliation":[{"name":"Huazhong University of Science and Technology & Zhejiang Lab, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-8056-0309","authenticated-orcid":false,"given":"Sitong","family":"Lu","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology & Zhejiang Lab, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2139-6465","authenticated-orcid":false,"given":"Zhiyuan","family":"Shao","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology & Zhejiang Lab, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6302-813X","authenticated-orcid":false,"given":"Xiaofei","family":"Liao","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3934-7605","authenticated-orcid":false,"given":"Hai","family":"Jin","sequence":"additional","affiliation":[{"name":"Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,4,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC47752.2019.9041977"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293901"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00054"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2049662.2049663"},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of Annual International Symposium on Computer Architecture","author":"Keith","unstructured":"Keith I. Farkas and Norman P. Jouppi. 1994. Complexity\/Performance Tradeoffs with Non-Blocking Loads. In Proceedings of Annual International Symposium on Computer Architecture. Chicago, IL, USA, 211--222."},{"key":"e_1_3_2_1_6_1","volume-title":"Proceedings of International Conference on Reconfigurable Computing and FPGAs. Cancun","author":"Santana Gil A. D.","year":"2010","unstructured":"A. D. Santana Gil, Jos\u00e9 Ignacio Benavides Ben'i tez, Manuel Hernandez Calvi n o, and Ezequiel Herruzo Gomez. 2010. Reconfigurable Cache Implemented on an FPGA. In Proceedings of International Conference on Reconfigurable Computing and FPGAs. Cancun, Quintana Roo, Mexico, 250--255."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3330345.3330390"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474061"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.79"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3075765"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3358192"},{"key":"e_1_3_2_1_12_1","volume-title":"Proceedings of Annual Symposium on Computer Architecture","author":"Kroft David","year":"1981","unstructured":"David Kroft. 1981. Lockup-Free Instruction Fetch\/Prefetch Cache Organization. In Proceedings of Annual Symposium on Computer Architecture. Minneapolis, Minnesota, USA, 81--88."},{"key":"e_1_3_2_1_13_1","unstructured":"Sheng Li Ke Chen Jay B. Brockman and Norman P. Jouppi. 2011. Performance impacts of non-blocking caches in out-of-order processors. HPL Technical Reports (2011) 1--9. https:\/\/www.hpl.hp.com\/techreports\/2011\/HPL-2011--65.html"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"e_1_3_2_1_15_1","volume-title":"Proceedings of International Conference on Field programmable Logic and Applications","author":"Naylor Matthew","unstructured":"Matthew Naylor, Paul James Fox, A. Theodore Markettos, and Simon W. Moore. 2013. Managing the FPGA memory wall: Custom computing or vector processing?. In Proceedings of International Conference on Field programmable Logic and Applications. Porto, Portugal, 1--6."},{"key":"e_1_3_2_1_16_1","volume-title":"Proceedings of IEEE\/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems","author":"Nguyen Tan","unstructured":"Tan Nguyen, Samuel Williams, Marco Siracusa, Colin MacLean, Douglas Doerfler, and Nicholas J. Wright. 2020. The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing. In Proceedings of IEEE\/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems. Atlanta, GA, USA, 8--19."},{"key":"e_1_3_2_1_17_1","volume-title":"Proceedings of Annual IEEE\/ACM International Symposium on Microarchitecture. ACM","author":"Power Jason","unstructured":"Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. 2013. Heterogeneous system coherence for integrated CPU-GPU systems. In Proceedings of Annual IEEE\/ACM International Symposium on Microarchitecture. ACM, Davis, CA, USA, 457--467."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1988.44672"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450150"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.44"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196053"},{"key":"e_1_3_2_1_22_1","unstructured":"Xilinx. 2019. Alveo U280 Data Center Accelerator Card. https:\/\/www.xilinx.com\/products\/boards-and-kits\/alveo\/u280.html"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"}],"event":{"name":"FPGA '24: The 2024 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey CA USA","acronym":"FPGA '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2024 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3626202.3637571","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3626202.3637571","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T22:03:57Z","timestamp":1755900237000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3626202.3637571"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4]]},"references-count":23,"alternative-id":["10.1145\/3626202.3637571","10.1145\/3626202"],"URL":"https:\/\/doi.org\/10.1145\/3626202.3637571","relation":{},"subject":[],"published":{"date-parts":[[2024,4]]},"assertion":[{"value":"2024-04-02","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}