{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:37:47Z","timestamp":1773247067201,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,11,2]],"date-time":"2023-11-02T00:00:00Z","timestamp":1698883200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/https:\/\/doi.org\/10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["HR0011-18-2-0032"],"award-info":[{"award-number":["HR0011-18-2-0032"]}],"id":[{"id":"10.13039\/https:\/\/doi.org\/10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/https:\/\/doi.org\/10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-2110419"],"award-info":[{"award-number":["CCF-2110419"]}],"id":[{"id":"10.13039\/https:\/\/doi.org\/10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/https:\/\/doi.org\/10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-2112665"],"award-info":[{"award-number":["CCF-2112665"]}],"id":[{"id":"10.13039\/https:\/\/doi.org\/10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Logic Pathfinding Lab, Samsung Semiconductor Inc."},{"name":"C-DEN center"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,11,2]]},"DOI":"10.1145\/3632409.3640475","type":"proceedings-article","created":{"date-parts":[[2024,2,15]],"date-time":"2024-02-15T16:43:16Z","timestamp":1708015396000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9865-8390","authenticated-orcid":false,"given":"Chung-Kuan","family":"Cheng","sequence":"first","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4490-5018","authenticated-orcid":false,"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0965-7247","authenticated-orcid":false,"given":"Bill","family":"Lin","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8219-8908","authenticated-orcid":false,"given":"Yucheng","family":"Wang","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-9542-8814","authenticated-orcid":false,"given":"Dooseok","family":"Yoon","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,2,15]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.3233\/FAIA201017"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3065639"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3184008"},{"key":"e_1_3_2_1_4_1","first-page":"1","volume-title":"Proc. IEEE Symposium on VLSI Technology","author":"Chidambaram C.","year":"2021","unstructured":"C. Chidambaram, et al., \"A Novel Framework for DTCO: Fast and Automatic Routability Assessment with Machine Learning for Sub-3nm Technology Options\", Proc. IEEE Symposium on VLSI Technology, 2021, pp. 1--2."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3334591"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218532"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3225209.3225210"},{"key":"e_1_3_2_1_8_1","volume-title":"University of California","author":"Lee D.","year":"2022","unstructured":"D. Lee, \"Logical Reasoning Techniques for VLSI Applications\", Ph.D. Dissertation, University of California, San Diego, 2022."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3037885"},{"key":"e_1_3_2_1_10_1","first-page":"707","article-title":"Binary Codes Capable of Correcting Deletions, Insertions, and Reversals","volume":"10","author":"Levenshtein V. I.","year":"1965","unstructured":"V. I. Levenshtein, \"Binary Codes Capable of Correcting Deletions, Insertions, and Reversals\", Soviet physics. Doklady 10 (1965), pp. 707--710.","journal-title":"Doklady"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2157076"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"e_1_3_2_1_13_1","first-page":"112","volume-title":"Proc. Symposium on VLSI Technology","author":"Northrop G.","year":"2011","unstructured":"G. Northrop. \"Design Technology Co-optimization in Technology Definition for 22nm and Beyond\", Proc. Symposium on VLSI Technology, 2011, pp. 112--113."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3299902.3309752"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3220339"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203889"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2399439"},{"key":"e_1_3_2_1_18_1","volume-title":"Proc. Design for Manufacturability through Design-Process Integration XI 10148","author":"Liebmann L.","year":"2017","unstructured":"L. Liebmann, et al., \"Exploiting regularity: breakthroughs in sub-7nm place-and-route\", Proc. Design for Manufacturability through Design-Process Integration XI 10148, SPIE, 2017"},{"key":"e_1_3_2_1_19_1","unstructured":"SMTCellUCSD: Cell Layout Generation for DTCO\/STCO Exploration Toolkit. https:\/\/github.com\/ckchengucsd\/SMTCellUCSD"},{"key":"e_1_3_2_1_20_1","unstructured":"ASAP7 PDK and Cell Libraries. https:\/\/github.com\/The-OpenROAD-Project\/asap7"},{"key":"e_1_3_2_1_21_1","unstructured":"Cadence Innovus User Guide. https:\/\/www.cadence.com"}],"event":{"name":"SLIP '23: 2023 ACM International Workshop on System-Level Interconnect Pathfinding","location":"San Francisco CA USA","acronym":"SLIP '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3632409.3640475","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3632409.3640475","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:45:43Z","timestamp":1750178743000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3632409.3640475"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11,2]]},"references-count":21,"alternative-id":["10.1145\/3632409.3640475","10.1145\/3632409"],"URL":"https:\/\/doi.org\/10.1145\/3632409.3640475","relation":{},"subject":[],"published":{"date-parts":[[2023,11,2]]},"assertion":[{"value":"2024-02-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}