{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:43:18Z","timestamp":1755999798891,"version":"3.41.0"},"reference-count":94,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2024,4,30]],"date-time":"2024-04-30T00:00:00Z","timestamp":1714435200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"crossref","award":["EXC 2092 CASA 390781972"],"award-info":[{"award-number":["EXC 2092 CASA 390781972"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2024,6,30]]},"abstract":"<jats:p>\n            Field Programmable Gate Arrays (FPGAs) have become increasingly popular in computing platforms. With recent advances in bitstream format reverse engineering, the scientific community has widely explored static FPGA security threats. For example, it is now possible to convert a bitstream to a netlist, revealing design information, and apply modifications to the static bitstream based on this knowledge. However, a systematic study of the influence of the bitstream format understanding in regards to the security aspects of the dynamic configuration process, particularly for Xilinx\u2019s Internal Configuration Access Port (ICAP), is lacking. This article fills this gap by comprehensively analyzing the security implications of ICAP interfaces, which primarily support dynamic partial reconfiguration. We delve into the Xilinx bitstream file format, identify misconceptions in official documentation, and propose novel configuration (attack) primitives based on dynamic reconfiguration, i.e., create\/read\/update\/delete circuits in the FPGA, without requiring pre-definition during the design phase. Our primitives are consolidated in a novel\n            <jats:italic>Stealthy Reconfigurable Adaptive Trojan<\/jats:italic>\n            framework to conceal Trojans and evade state-of-the-art netlist reverse engineering methods. As FPGAs become integral to modern cloud computing, this research presents crucial insights on potential security risks, including the possibility of a malicious tenant or provider altering or spying on another tenant\u2019s configuration undetected.\n          <\/jats:p>","DOI":"10.1145\/3633204","type":"journal-article","created":{"date-parts":[[2023,11,17]],"date-time":"2023-11-17T12:13:21Z","timestamp":1700223201000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["On the Malicious Potential of Xilinx\u2019s Internal Configuration Access Port (ICAP)"],"prefix":"10.1145","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2449-1134","authenticated-orcid":false,"given":"Nils","family":"Albartus*","sequence":"first","affiliation":[{"name":"Max Planck Institute for Security and Privacy, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0685-2541","authenticated-orcid":false,"given":"Maik","family":"Ender*","sequence":"additional","affiliation":[{"name":"Max Planck Institute for Security and Privacy, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-3006-7846","authenticated-orcid":false,"given":"Jan-Niklas","family":"M\u00f6ller*","sequence":"additional","affiliation":[{"name":"Max Planck Institute for Security and Privacy, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4266-7108","authenticated-orcid":false,"given":"Marc","family":"Fyrbiak","sequence":"additional","affiliation":[{"name":"Max Planck Institute for Security and Privacy, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8681-2277","authenticated-orcid":false,"given":"Christof","family":"Paar","sequence":"additional","affiliation":[{"name":"Max Planck Institute for Security and Privacy, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0591-7566","authenticated-orcid":false,"given":"Russell","family":"Tessier","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,4,30]]},"reference":[{"key":"e_1_3_3_2_2","unstructured":"Xilinx. 2021. XAPP1098 - Developing Tamper-Resistant Designs with UltraScale and UltraScale+ FPGAs. https:\/\/docs.xilinx.com\/v\/u\/en-US\/xapp1098-tamper-resist-designs"},{"key":"e_1_3_3_3_2","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i4.309-336"},{"key":"e_1_3_3_4_2","unstructured":"Chips Alliance. [n. d.] Project U-Ray. Retrieved from https:\/\/github.com\/f4pga\/prjuray"},{"key":"e_1_3_3_5_2","unstructured":"Chips Alliance. [n. d.] Project X-Ray. Retrieved from https:\/\/github.com\/f4pga\/prjxray"},{"key":"e_1_3_3_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702704"},{"volume-title":"Amazon EC2 F1","key":"e_1_3_3_7_2","unstructured":"Amazon. [n. d.] Amazon EC2 F1. Amazon AWS. Retrieved from https:\/\/aws.amazon.com\/ec2\/instance-types\/f1\/"},{"key":"e_1_3_3_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3338508.3359575"},{"key":"e_1_3_3_9_2","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-021-00268-5"},{"key":"e_1_3_3_10_2","unstructured":"Microsoft Azure. [n. d.] NP-series\u2014Azure Virtual Machines. Retrieved from https:\/\/learn.microsoft.com\/en-us\/azure\/virtual-machines\/np-series"},{"key":"e_1_3_3_11_2","doi-asserted-by":"publisher","unstructured":"Sebastian Banescu and Alexander Pretschner. 2018. A tutorial on software obfuscation. In Advances in Computers Vol. 108. Elsevier 283\u2013353. 10.1016\/bs.adcom.2017.09.004","DOI":"10.1016\/bs.adcom.2017.09.004"},{"issue":"3","key":"e_1_3_3_12_2","first-page":"34","article-title":"The future of FPGA acceleration in datacenters and the cloud","volume":"15","author":"Bobda Christophe","year":"2022","unstructured":"Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin Herbordt, Hafsah Shahzad, Peter Hofste, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, and Russell Tessier. 2022. The future of FPGA acceleration in datacenters and the cloud. Trans. Reconfig. Technol. Syst. 15, 3, Article 34 (Sep.2022), 42 pages.","journal-title":"Trans. Reconfig. Technol. Syst."},{"key":"e_1_3_3_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3071607"},{"key":"e_1_3_3_14_2","first-page":"12","article-title":"How to add features and fix bugs\u2014Remotely","volume":"33","author":"Branca Tom","year":"1999","unstructured":"Tom Branca. 1999. How to add features and fix bugs\u2014Remotely. Xcell, Vol. 33, 12\u201314. https:\/\/www.xilinx.com\/publications\/archives\/xcell\/Xcell33.pdf","journal-title":"Xcell"},{"key":"e_1_3_3_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8740844"},{"issue":"6","key":"e_1_3_3_16_2","first-page":"58:1\u201358:31","article-title":"Toward a human-readable state machine extraction","volume":"27","author":"Brunner Michaela","year":"2022","unstructured":"Michaela Brunner, Alexander Hepp, Johanna Baehr, and Georg Sigl. 2022. Toward a human-readable state machine extraction. ACM Trans. Design Autom. Electr. Syst. 27, 6 (2022), 58:1\u201358:31.","journal-title":"ACM Trans. Design Autom. Electr. Syst."},{"key":"e_1_3_3_17_2","first-page":"471","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE\u201915)","author":"\u00c7akir Bur\u00e7in","year":"2015","unstructured":"Bur\u00e7in \u00c7akir and Sharad Malik. 2015. Hardware trojan detection for gate-level ICs using signal correlation based clustering. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE\u201915), Wolfgang Nebel and David Atienza (Eds.). ACM, 471\u2013476. http:\/\/dl.acm.org\/citation.cfm?id=2755860"},{"key":"e_1_3_3_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/CCE.2006.350791"},{"key":"e_1_3_3_19_2","unstructured":"Xilinx Corporation. FPGA Design Security. Retrieved from https:\/\/www.xilinx.com\/support\/documentation-navigation\/design-hubs\/dh0082-fpga-security-hub.html"},{"key":"e_1_3_3_20_2","doi-asserted-by":"crossref","unstructured":"Defense Science Board Washington DC. 2005. Report of the Defense Science Board Task Force on High Performance Microchip Supply.","DOI":"10.21236\/ADA435837"},{"key":"e_1_3_3_21_2","doi-asserted-by":"crossref","unstructured":"Paul Dempsey. [n. d.] Teardown: HTC Vive Pro VR headset. Retrieved from https:\/\/eandt.theiet.org\/content\/articles\/2018\/05\/teardown-htc-vive-pro-vr-headset\/","DOI":"10.1049\/et.2018.0529"},{"key":"e_1_3_3_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/2771283"},{"key":"e_1_3_3_23_2","first-page":"1","volume-title":"Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201922)","author":"Ender Maik","year":"2022","unstructured":"Maik Ender, Gregor Leander, Amir Moradi, and Christof Paar. 2022. A cautionary note on protecting Xilinx\u2019 UltraScale(+) bitstream encryption and authentication engine. In Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201922). IEEE, 1\u20139."},{"key":"e_1_3_3_24_2","first-page":"1803","volume-title":"Proceedings of the 29th USENIX Security Symposium (USENIX Security\u201920)","author":"Ender Maik","year":"2020","unstructured":"Maik Ender, Amir Moradi, and Christof Paar. 2020. The unpatchable silicon: A full break of the bitstream encryption of Xilinx 7-series FPGAs. In Proceedings of the 29th USENIX Security Symposium (USENIX Security\u201920), Srdjan Capkun and Franziska Roesner (Eds.). USENIX Association, 1803\u20131819."},{"key":"e_1_3_3_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3288742"},{"key":"e_1_3_3_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2649520"},{"key":"e_1_3_3_27_2","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2018.i3.293-330"},{"key":"e_1_3_3_28_2","article-title":"HAL-The missing piece of the puzzle for hardware reverse engineering, trojan detection and insertion","author":"Fyrbiak Marc","year":"2018","unstructured":"Marc Fyrbiak, Sebastian Wallat, Pawel Swierczynski, Max Hoffmann, Sebastian Hoppach, Matthias Wilhelm, Tobias Weidlich, Russell Tessier, and Christof Paar. 2018. HAL-The missing piece of the puzzle for hardware reverse engineering, trojan detection and insertion. IEEE Trans. Depend. Secure Comput. (2018).","journal-title":"IEEE Trans. Depend. Secure Comput."},{"key":"e_1_3_3_29_2","doi-asserted-by":"publisher","DOI":"10.5555\/2682923.2682943"},{"key":"e_1_3_3_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/2362374.2362380"},{"key":"e_1_3_3_31_2","article-title":"Leakier wires: Exploiting FPGA long wires for covert- and side-channel attacks","author":"Giechaskiel Ilias","year":"2019","unstructured":"Ilias Giechaskiel, Ken Eguro, and Kasper Rasmussen. 2019. Leakier wires: Exploiting FPGA long wires for covert- and side-channel attacks. Trans. Reconfig. Technol. Syst. (2019).","journal-title":"Trans. Reconfig. Technol. Syst."},{"key":"e_1_3_3_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2848460"},{"key":"e_1_3_3_33_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_20"},{"key":"e_1_3_3_34_2","unstructured":"HAL. HAL\u2014The Hardware Analyzer. Retrieved from https:\/\/github.com\/emsec\/hal"},{"key":"e_1_3_3_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.139"},{"issue":"6","key":"e_1_3_3_36_2","article-title":"Overcoming an untrusted computing base: Detecting and removing malicious hardware automatically","volume":"35","author":"Hicks Matthew","year":"2010","unstructured":"Matthew Hicks, Murph Finnicum, Samuel T. King, Milo M. K. Martin, and Jonathan M. Smith. 2010. Overcoming an untrusted computing base: Detecting and removing malicious hardware automatically. login Usenix Mag. 35, 6 (2010). https:\/\/www.usenix.org\/publications\/login\/december-2010-volume-35-number-6\/overcoming-untrusted-computing-base-detecting","journal-title":"login Usenix Mag."},{"key":"e_1_3_3_37_2","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2021.i1.82-108"},{"key":"e_1_3_3_38_2","volume-title":"Proceedings of the 13th USENIX Workshop on Offensive Technologies (WOOT\u201919)","author":"Kataria Jatin","year":"2019","unstructured":"Jatin Kataria, Rick Housley, Joseph Pantoga, and Ang Cui. 2019. Defeating Cisco trust anchor: A Case-study of recent advancements in direct fpga bitstream manipulation. In Proceedings of the 13th USENIX Workshop on Offensive Technologies (WOOT\u201919), Alex Gantman and Cl\u00e9mentine Maurice (Eds.). USENIX Association. https:\/\/www.usenix.org\/conference\/woot19\/presentation\/kataria"},{"key":"e_1_3_3_39_2","first-page":"107","volume-title":"Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation","author":"Khawaja Ahmed","year":"2018","unstructured":"Ahmed Khawaja, Joshua Landgraf, Rohith Prakash, Michael Wei, Eric Schkufza, and Christopher J. Rossbach. 2018. Sharing, protection, and compatibility for reconfigurable fabric with AmorphOS. In Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation. 107\u2013127."},{"key":"e_1_3_3_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942094"},{"key":"e_1_3_3_41_2","doi-asserted-by":"publisher","DOI":"10.1145\/3328222"},{"key":"e_1_3_3_42_2","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967054"},{"key":"e_1_3_3_43_2","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2021.i3.441-464"},{"key":"e_1_3_3_44_2","doi-asserted-by":"publisher","DOI":"10.1145\/3402937"},{"key":"e_1_3_3_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2013.6581568"},{"key":"e_1_3_3_46_2","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415694"},{"key":"e_1_3_3_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2169667"},{"key":"e_1_3_3_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT56656.2022.9974549"},{"key":"e_1_3_3_49_2","doi-asserted-by":"publisher","DOI":"10.1145\/3462329"},{"key":"e_1_3_3_50_2","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-018-0043-4"},{"key":"e_1_3_3_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428086"},{"key":"e_1_3_3_52_2","doi-asserted-by":"publisher","DOI":"10.31399\/asm.cp.istfa2016p0342"},{"volume-title":"Microsoft Azure Machine Learning","year":"2023","key":"e_1_3_3_53_2","unstructured":"Microsoft. 2023. Microsoft Azure Machine Learning. Microsoft. Retrieved from https:\/\/azure.microsoft.com\/en-us\/pricing\/details\/machine-learning\/"},{"key":"e_1_3_3_54_2","doi-asserted-by":"publisher","DOI":"10.1145\/2046707.2046722"},{"key":"e_1_3_3_55_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-27954-6_1"},{"key":"e_1_3_3_56_2","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435282"},{"key":"e_1_3_3_57_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-43283-0_5"},{"key":"e_1_3_3_58_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380654"},{"key":"e_1_3_3_59_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927114"},{"key":"e_1_3_3_60_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL57034.2022.00085"},{"key":"e_1_3_3_61_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00038"},{"key":"e_1_3_3_62_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00046"},{"key":"e_1_3_3_63_2","first-page":"9:1\u20139:24","article-title":"Mitigating voltage attacks in multi-tenant FPGAs","author":"Provelengios George","year":"2021","unstructured":"George Provelengios, Daniel E. Holcomb, and Russell Tessier. 2021. Mitigating voltage attacks in multi-tenant FPGAs. ACM Trans. Reconfig. Technol. Syst. (Jul.2021), 9:1\u20139:24.","journal-title":"ACM Trans. Reconfig. Technol. Syst."},{"key":"e_1_3_3_64_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-78890-6_24"},{"key":"e_1_3_3_65_2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00016"},{"key":"e_1_3_3_66_2","doi-asserted-by":"publisher","DOI":"10.1109\/IAdCC.2014.6779423"},{"key":"e_1_3_3_67_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3063306"},{"key":"e_1_3_3_68_2","unstructured":"SecWorks. Secworks AES Core with On-The-Fly Keygen. Retrieved from https:\/\/github.com\/secworks\/aes\/tree\/on_the_fly_keygen"},{"key":"e_1_3_3_69_2","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2021.i4.412-446"},{"key":"e_1_3_3_70_2","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503081"},{"key":"e_1_3_3_71_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2399455"},{"key":"e_1_3_3_72_2","doi-asserted-by":"publisher","DOI":"10.1145\/2629462"},{"key":"e_1_3_3_73_2","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3134039"},{"key":"e_1_3_3_74_2","unstructured":"Stephanie Tapp Xilinx. [n. d.]. XAPP1230 - Configuration Readback Capture in UltraScale FPGAs. Retrieved from https:\/\/docs.xilinx.com\/v\/u\/en-US\/xapp1230-configuration-readback-capture"},{"key":"e_1_3_3_75_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"e_1_3_3_76_2","unstructured":"Aaron Tilley. This Mysterious Chip In The iPhone 7 Could Be Key To Apple\u2019s AI Push. Retrieved from https:\/\/www.forbes.com\/sites\/aarontilley\/2016\/10\/17\/iphone-7-fpga-chip-artificial-intelligence\/?sh=4158ca3d3c69"},{"key":"e_1_3_3_77_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCS.2017.19"},{"key":"e_1_3_3_78_2","doi-asserted-by":"publisher","DOI":"10.5555\/1843424.1843439"},{"key":"e_1_3_3_79_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP40001.2021.00052"},{"key":"e_1_3_3_80_2","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516654"},{"key":"e_1_3_3_81_2","unstructured":"Xilinx. 2023. UG470\u20147 Series FPGAs Configuration. Retrieved from https:\/\/docs.xilinx.com\/r\/en-US\/ug470_7Series_Config"},{"key":"e_1_3_3_82_2","unstructured":"Xilinx. 2023. UG570\u2014UltraScale Architecture Configuration. Retrieved from https:\/\/docs.xilinx.com\/v\/u\/en-US\/ug570-ultrascale-configuration"},{"key":"e_1_3_3_83_2","unstructured":"Xilinx. 2022. UG909\u2014Vivado Design Suite User Guide: Dynamic Function eXchange. Retrieved from https:\/\/docs.xilinx.com\/r\/en-US\/ug909-vivado-partial-reconfiguration"},{"volume-title":"42946\u2014Design Advisory Master Answer Record for Kintex-7 FPGA","year":"2023","key":"e_1_3_3_84_2","unstructured":"Xilinx. 2023. 42946\u2014Design Advisory Master Answer Record for Kintex-7 FPGA. Xilinx Corporation."},{"volume-title":"52881\u2014Configuration - BitStream Encryption\u2014How to create and program an encrypted bitstream","year":"2023","key":"e_1_3_3_85_2","unstructured":"Xilinx. 2023. 52881\u2014Configuration - BitStream Encryption\u2014How to create and program an encrypted bitstream. https:\/\/support.xilinx.com\/s\/article\/52881?language=en_US"},{"volume-title":"73541\u2014Design Advisory for 7 Series\/Virtex-6 FPGAs: Defeating Bitstream Encryption","year":"2023","key":"e_1_3_3_86_2","unstructured":"Xilinx. 2023. 73541\u2014Design Advisory for 7 Series\/Virtex-6 FPGAs: Defeating Bitstream Encryption. Xilinx Corporation."},{"key":"e_1_3_3_87_2","unstructured":"Xilinx. 2009. Security Monitor IP. Retrieved from https:\/\/www.xilinx.com\/support\/documents\/product-briefs\/security-monitor-ip-core-product-brief.pdf"},{"key":"e_1_3_3_88_2","unstructured":"Xilinx. 2021. XAPP1098 - Developing Tamper-Resistant Designs with UltraScale and UltraScale+ FPGAs. https:\/\/docs.xilinx.com\/v\/u\/en-US\/xapp1098-tamper-resist-designs"},{"key":"e_1_3_3_89_2","unstructured":"Xilinx. 2017. UG908 - Vivado Design Suite User Guide Programming and Debugging. https:\/\/docs.xilinx.com\/v\/u\/2017.1-English\/ug908-vivado-programming-debugging"},{"key":"e_1_3_3_90_2","unstructured":"Xilinx. 2005. UG002 - Virtex-II Platform FPGA User Guide 002. https:\/\/docs.xilinx.com\/v\/u\/en-US\/ug002"},{"key":"e_1_3_3_91_2","unstructured":"Xilinx. 2015. XCN15038 - RSA Authentication and Supporting Configuration Modes."},{"key":"e_1_3_3_92_2","unstructured":"Xilinx. 2021. XAPP1239 - Using Encryption to Secure a 7 Series FPGA Bitstream."},{"key":"e_1_3_3_93_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2422836"},{"issue":"1","key":"e_1_3_3_94_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3409113","article-title":"CoNFV: A heterogeneous platform for scalable network function virtualization","volume":"14","author":"Zhang Xuzhi","year":"2020","unstructured":"Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, and Russell Tessier. 2020. CoNFV: A heterogeneous platform for scalable network function virtualization. ACM Trans. Reconfig. Technol. Syst. 14, 1 (112020), 1\u201329.","journal-title":"ACM Trans. Reconfig. Technol. Syst."},{"key":"e_1_3_3_95_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2018.00049"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3633204","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3633204","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:54:00Z","timestamp":1750287240000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3633204"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,30]]},"references-count":94,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2024,6,30]]}},"alternative-id":["10.1145\/3633204"],"URL":"https:\/\/doi.org\/10.1145\/3633204","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2024,4,30]]},"assertion":[{"value":"2023-06-30","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-10-29","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-04-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}