{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T01:04:33Z","timestamp":1773277473685,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":101,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Centers of Academic Excellence in Cybersecurity","award":["H98230-22-1-0307"],"award-info":[{"award-number":["H98230-22-1-0307"]}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2237238"],"award-info":[{"award-number":["2237238"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,7]]},"DOI":"10.1145\/3634737.3637644","type":"proceedings-article","created":{"date-parts":[[2024,6,28]],"date-time":"2024-06-28T11:51:38Z","timestamp":1719575498000},"page":"1584-1599","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Building Your Own Trusted Execution Environments Using FPGA"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-5264-7962","authenticated-orcid":false,"given":"Md","family":"Armanuzzaman","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, University at Buffalo, Buffalo, NY, United States of America"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6833-3598","authenticated-orcid":false,"given":"Ahmad-Reza","family":"Sadeghi","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Technische Universit\u00e4t Darmstadt, Darmstadt, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4930-5556","authenticated-orcid":false,"given":"Ziming","family":"Zhao","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, University at Buffalo, Buffalo, NY, United States of America"}]}],"member":"320","published-online":{"date-parts":[[2024,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"\" IACR Cryptol. ePrint Arch","author":"Costan V.","year":"2016","unstructured":"V. Costan and S. Devadas, \"Intel SGX Explained.,\" IACR Cryptol. ePrint Arch., 2016."},{"key":"e_1_3_2_1_2_1","volume-title":"Demystifying arm trustzone: A comprehensive survey,\" ACM Computing Surveys (CSUR)","author":"Pinto S.","year":"2019","unstructured":"S. Pinto and N. Santos, \"Demystifying arm trustzone: A comprehensive survey,\" ACM Computing Surveys (CSUR), 2019."},{"key":"e_1_3_2_1_3_1","volume-title":"CURE: A Security Architecture with CUstomizable and Resilient Enclaves,\" in USENIX Security Symposium","author":"Bahmani R.","year":"2021","unstructured":"R. Bahmani, F. Brasser, G. Dessouky, P. Jauernig, M. Klimmek, A.-R. Sadeghi, and E. Stapf, \"CURE: A Security Architecture with CUstomizable and Resilient Enclaves,\" in USENIX Security Symposium, 2021."},{"key":"e_1_3_2_1_4_1","volume-title":"Hypervision across worlds: Real-time kernel protection from the arm trustzone secure world,\" in ACM Conference on Computer and Communications Security (CCS)","author":"Azab A. M.","year":"2014","unstructured":"A. M. Azab, P. Ning, J. Shah, Q. Chen, R. Bhutkar, G. Ganesh, J. Ma, and W. Shen, \"Hypervision across worlds: Real-time kernel protection from the arm trustzone secure world,\" in ACM Conference on Computer and Communications Security (CCS), 2014."},{"key":"e_1_3_2_1_5_1","volume-title":"Sprobes: Enforcing Kernel Code Integrity on the TrustZone Architecture,\" in Mobile Security Technologies Workshop (MoST)","author":"Ge X.","year":"2014","unstructured":"X. Ge and T. Jaeger, \"Sprobes: Enforcing Kernel Code Integrity on the TrustZone Architecture,\" in Mobile Security Technologies Workshop (MoST), 2014."},{"key":"e_1_3_2_1_6_1","volume-title":"SCONE: Secure linux containers with intel SGX,\" in USENIX symposium on Operating Systems Design and Implementation (OSDI)","author":"Arnautov S.","year":"2016","unstructured":"S. Arnautov, B. Trach, F. Gregor, T. Knauth, A. Martin, C. Priebe, J. Lind, D. Muthukumaran, D. O'keeffe, M. L. Stillwell, et al., \"SCONE: Secure linux containers with intel SGX,\" in USENIX symposium on Operating Systems Design and Implementation (OSDI), 2016."},{"key":"e_1_3_2_1_7_1","volume-title":"Graphene-sgx: A practical library OS for unmodified applications on SGX,\" in USENIX Annual Technical Conference (ATC)","author":"Tsai C.-C.","year":"2017","unstructured":"C.-C. Tsai, D. E. Porter, and M. Vij, \"Graphene-sgx: A practical library OS for unmodified applications on SGX,\" in USENIX Annual Technical Conference (ATC), 2017."},{"key":"e_1_3_2_1_8_1","volume-title":"Using ARM TrustZone to build a trusted language runtime for mobile applications,\" in International conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)","author":"Santos N.","year":"2014","unstructured":"N. Santos, H. Raj, S. Saroiu, and A. Wolman, \"Using ARM TrustZone to build a trusted language runtime for mobile applications,\" in International conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2014."},{"key":"e_1_3_2_1_9_1","author":"Baumann A.","year":"2015","unstructured":"A. Baumann, M. Peinado, and G. Hunt, \"Shielding applications from an untrusted cloud with haven,\" ACM Transactions on Computer Systems (TOCS), 2015.","journal-title":"\"Shielding applications from an untrusted cloud with haven,\" ACM Transactions on Computer Systems (TOCS)"},{"key":"e_1_3_2_1_10_1","volume-title":"Glamdring: Automatic application partitioning for intel SGX,\" in USENIX Annual Technical Conference (ATC)","author":"Lind J.","year":"2017","unstructured":"J. Lind, C. Priebe, D. Muthukumaran, D. O'Keeffe, P.-L. Aublin, F. Kelbert, T. Reiher, D. Goltzsche, D. Eyers, R. Kapitza, et al., \"Glamdring: Automatic application partitioning for intel SGX,\" in USENIX Annual Technical Conference (ATC), 2017."},{"key":"e_1_3_2_1_11_1","volume-title":"VC3: Trustworthy data analytics in the cloud using SGX,\" in IEEE symposium on Security and Privacy (S&P)","author":"Schuster F.","year":"2015","unstructured":"F. Schuster, M. Costa, C. Fournet, C. Gkantsidis, M. Peinado, G. Mainar-Ruiz, and M. Russinovich, \"VC3: Trustworthy data analytics in the cloud using SGX,\" in IEEE symposium on Security and Privacy (S&P), 2015."},{"key":"e_1_3_2_1_12_1","volume-title":"SoK: Understanding the Prevailing Security Vulnerabilities in TrustZone-assisted TEE Systems,\" in IEEE symposium on Security and Privacy (S&P)","author":"Cerdeira D.","year":"2020","unstructured":"D. Cerdeira, N. Santos, P. Fonseca, and S. Pinto, \"SoK: Understanding the Prevailing Security Vulnerabilities in TrustZone-assisted TEE Systems,\" in IEEE symposium on Security and Privacy (S&P), 2020."},{"key":"e_1_3_2_1_13_1","volume-title":"Breaking trustzone memory isolation through malicious hardware on a modern fpga-soc,\" in ACM Workshop on Attacks and Solutions in Hardware Security Workshop (ASHES)","author":"Gross M.","year":"2019","unstructured":"M. Gross, N. Jacob, A. Zankl, and G. Sigl, \"Breaking trustzone memory isolation through malicious hardware on a modern fpga-soc,\" in ACM Workshop on Attacks and Solutions in Hardware Security Workshop (ASHES), 2019."},{"key":"e_1_3_2_1_14_1","author":"Schneider M.","year":"2022","unstructured":"M. Schneider, A. Dhar, I. Puddu, K. Kostiainen, and S. Capkun, \"Composite Enclaves: Towards Disaggregated Trusted Execution,\" IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022.","journal-title":"\"Composite Enclaves: Towards Disaggregated Trusted Execution,\" IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"e_1_3_2_1_15_1","volume-title":"TruSpy: Cache Side-Channel Information Leakage from the Secure World on ARM Devices,\" IACR Cryptology ePrint Archive","author":"Zhang N.","year":"2016","unstructured":"N. Zhang, K. Sun, D. Shands, W. Lou, and Y. T. Hou, \"TruSpy: Cache Side-Channel Information Leakage from the Secure World on ARM Devices,\" IACR Cryptology ePrint Archive, 2016."},{"key":"e_1_3_2_1_16_1","volume-title":"Novel cross-world covert channels on arm trustzone,\" in Annual Computer Security Applications Conference (ACSAC)","author":"Cho H.","year":"2018","unstructured":"H. Cho, P. Zhang, D. Kim, J. Park, C.-H. Lee, Z. Zhao, A. Doup\u00e9, and G.-J. Ahn, \"Prime+Count: Novel cross-world covert channels on arm trustzone,\" in Annual Computer Security Applications Conference (ACSAC), 2018."},{"key":"e_1_3_2_1_17_1","volume-title":"SGX cache attacks are practical,\" in USENIX Workshop on Offensive Technologies","author":"Brasser F.","year":"2017","unstructured":"F. Brasser, U. M\u00fcller, A. Dmitrienko, K. Kostiainen, S. Capkun, and A.-R. Sadeghi, \"Software grand exposure: SGX cache attacks are practical,\" in USENIX Workshop on Offensive Technologies, 2017."},{"key":"e_1_3_2_1_18_1","volume-title":"Return-oriented flush-reload side channels on arm and their implications for android devices,\" in ACM Conference on Computer and Communications Security (CCS)","author":"Zhang X.","year":"2016","unstructured":"X. Zhang, Y. Xiao, and Y. Zhang, \"Return-oriented flush-reload side channels on arm and their implications for android devices,\" in ACM Conference on Computer and Communications Security (CCS), 2016."},{"key":"e_1_3_2_1_19_1","volume-title":"Defeating the cachekit attack,\" in Workshop on Attacks and Solutions in Hardware Security","author":"Gutierrez M.","year":"2018","unstructured":"M. Gutierrez, Z. Zhao, A. Doup\u00e9, Y. Shoshitaishvili, and G.-J. Ahn, \"Cachelight: Defeating the cachekit attack,\" in Workshop on Attacks and Solutions in Hardware Security, 2018."},{"key":"e_1_3_2_1_20_1","volume-title":"SANCTUARY: ARMing TrustZone with User-space Enclaves.,\" in Network and Distributed System Security Symposium (NDSS)","author":"Brasser F.","year":"2019","unstructured":"F. Brasser, D. Gens, P. Jauernig, A.-R. Sadeghi, and E. Stapf, \"SANCTUARY: ARMing TrustZone with User-space Enclaves.,\" in Network and Distributed System Security Symposium (NDSS), 2019."},{"key":"e_1_3_2_1_21_1","volume-title":"HECTOR-V: A heterogeneous CPU architecture for a secure RISC-V execution environment,\" in ACM Asia Conference on Computer and Communications Security (AsiaCCS)","author":"Nasahl P.","year":"2021","unstructured":"P. Nasahl, R. Schilling, M. Werner, and S. Mangard, \"HECTOR-V: A heterogeneous CPU architecture for a secure RISC-V execution environment,\" in ACM Asia Conference on Computer and Communications Security (AsiaCCS), 2021."},{"key":"e_1_3_2_1_22_1","volume-title":"Graviton: Trusted execution environments on gpus,\" in USENIX symposium on Operating Systems Design and Implementation (OSDI)","author":"Volos S.","year":"2018","unstructured":"S. Volos, K. Vaswani, and R. Bruno, \"Graviton: Trusted execution environments on gpus,\" in USENIX symposium on Operating Systems Design and Implementation (OSDI), 2018."},{"key":"e_1_3_2_1_23_1","volume-title":"starting as early as","author":"Wilson J.","year":"2023","unstructured":"J. Wilson, \"AMD will infuse EPYC CPUs with Xilinx-based FPGA AI Engines, starting as early as 2023.\" https:\/\/wccftech.com\/amd-will-infuse-epyc-cpus-with-xilinx-based-fpga-ai-engines-starting-as-early-as-2023\/, -."},{"key":"e_1_3_2_1_24_1","unstructured":"\"Project Catapult.\" https:\/\/www.microsoft.com\/en-us\/research\/project\/project-catapult\/."},{"key":"e_1_3_2_1_25_1","unstructured":"\"Project Brainwave.\" https:\/\/www.microsoft.com\/en-us\/research\/project\/project-brainwave\/."},{"key":"e_1_3_2_1_26_1","unstructured":"\"Amazon EC2 documentation.\" https:\/\/docs.aws.amazon.com\/AWSEC2\/latest\/UserGuide\/DocumentHistory.html -."},{"key":"e_1_3_2_1_27_1","volume-title":"Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks,\" in ACM International Symposium on Field-Programmable Gate Arrays (FPGA)","author":"Zhang C.","year":"2015","unstructured":"C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong, \"Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks,\" in ACM International Symposium on Field-Programmable Gate Arrays (FPGA), 2015."},{"key":"e_1_3_2_1_28_1","volume-title":"Throughput-optimized opencl-based fpga accelerator for large-scale convolutional neural networks,\" in ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)","author":"Suda N.","year":"2016","unstructured":"N. Suda, V. Chandra, G. Dasika, A. Mohanty, Y. Ma, S. Vrudhula, J.-s. Seo, and Y. Cao, \"Throughput-optimized opencl-based fpga accelerator for large-scale convolutional neural networks,\" in ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2016."},{"key":"e_1_3_2_1_29_1","volume-title":"E-rnn: Design optimization for efficient recurrent neural networks in fpgas,\" in IEEE International Symposium on High Performance Computer Architecture (HPCA)","author":"Li Z.","year":"2019","unstructured":"Z. Li, C. Ding, S. Wang, W. Wen, Y. Zhuo, C. Liu, Q. Qiu, W. Xu, X. Lin, X. Qian, et al., \"E-rnn: Design optimization for efficient recurrent neural networks in fpgas,\" in IEEE International Symposium on High Performance Computer Architecture (HPCA), 2019."},{"key":"e_1_3_2_1_30_1","volume-title":"Fast elliptic curve cryptography on fpga,\" IEEE transactions on very large scale integration (VLSI) systems","author":"Chelton W. N.","year":"2008","unstructured":"W. N. Chelton and M. Benaissa, \"Fast elliptic curve cryptography on fpga,\" IEEE transactions on very large scale integration (VLSI) systems, 2008."},{"key":"e_1_3_2_1_31_1","volume-title":"High-performance fpga accelerator for sike,\" IEEE Transactions on Computers","author":"Elkhatib R.","year":"2021","unstructured":"R. Elkhatib, R. Azarderakhsh, and M. Mozaffari-Kermani, \"High-performance fpga accelerator for sike,\" IEEE Transactions on Computers, 2021."},{"key":"e_1_3_2_1_32_1","volume-title":"An fpga-based in-line accelerator for memcached,\" IEEE Computer Architecture Letters","author":"Lavasani M.","year":"2013","unstructured":"M. Lavasani, H. Angepat, and D. Chiou, \"An fpga-based in-line accelerator for memcached,\" IEEE Computer Architecture Letters, 2013."},{"key":"e_1_3_2_1_33_1","unstructured":"\"Open Cores.\" https:\/\/opencores.org\/."},{"key":"e_1_3_2_1_34_1","unstructured":"\"VexRiscv.\" https:\/\/github.com\/SpinalHDL\/VexRiscv 2022."},{"key":"e_1_3_2_1_35_1","unstructured":"\"Neo430.\" https:\/\/github.com\/stnolting\/neo430 2020."},{"key":"e_1_3_2_1_36_1","unstructured":"\"Microwatt.\" https:\/\/github.com\/antonblanchard\/microwatt."},{"key":"e_1_3_2_1_37_1","unstructured":"\"A2I.\" https:\/\/github.com\/openpower-cores\/a2i."},{"key":"e_1_3_2_1_38_1","unstructured":"\"A2O.\" https:\/\/github.com\/openpower-cores\/a2o."},{"key":"e_1_3_2_1_39_1","unstructured":"\"OpenSPARC T1 Softcore Processor.\" https:\/\/www.oracle.com\/servers\/technologies\/opensparc-t1-page.html."},{"key":"e_1_3_2_1_40_1","unstructured":"\"libreSOC.\" https:\/\/libre-soc.org\/."},{"key":"e_1_3_2_1_41_1","author":"Lysecky R.","year":"2009","unstructured":"R. Lysecky and F. Vahid, \"Design and implementation of a microblaze-based warp processor,\" ACM Transactions on Embedded Computing Systems (TECS), 2009.","journal-title":"\"Design and implementation of a microblaze-based warp processor,\" ACM Transactions on Embedded Computing Systems (TECS)"},{"key":"e_1_3_2_1_42_1","unstructured":"\"Intel NIOS softcore.\" https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/fpga\/nios-processor\/ 2020."},{"key":"e_1_3_2_1_43_1","volume-title":"Taiga: A new risc-v soft-processor framework enabling high performance cpu architectural features,\" in 2017 27th International Conference on Field Programmable Logic and Applications (FPL)","author":"Matthews E.","year":"2017","unstructured":"E. Matthews and L. Shannon, \"Taiga: A new risc-v soft-processor framework enabling high performance cpu architectural features,\" in 2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017."},{"key":"e_1_3_2_1_44_1","volume-title":"A catalog and in-hardware evaluation of open-source drop-in compatible risc-v softcore processors,\" in International Conference on ReConFigurable Computing and FPGAs (ReConFig)","author":"Heinz C.","year":"2019","unstructured":"C. Heinz, Y. Lavan, J. Hofmann, and A. Koch, \"A catalog and in-hardware evaluation of open-source drop-in compatible risc-v softcore processors,\" in International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2019."},{"key":"e_1_3_2_1_45_1","volume-title":"Verify: Evaluation of reliability using vhdl-models with embedded fault descriptions,\" in IEEE International Symposium on Fault Tolerant Computing","author":"Sieh V.","year":"1997","unstructured":"V. Sieh, O. Tschache, and F. Balbach, \"Verify: Evaluation of reliability using vhdl-models with embedded fault descriptions,\" in IEEE International Symposium on Fault Tolerant Computing, 1997."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"crossref","unstructured":"P. T. Breuer C. K. Delgado A. L. Marin N. Martinez Madrid and L. Sanchez Fernandez \"A refinement calculus for the synthesis of verified hardware descriptions in vhdl \" ACM Transactions on Programming Languages and Systems (TOPLAS) 1997.","DOI":"10.1145\/262004.262007"},{"key":"e_1_3_2_1_47_1","unstructured":"Xilinx \"Zynq-7000 SoC Technical Reference Manual.\" https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug585-Zynq-7000-TRM.pdf 2021."},{"key":"e_1_3_2_1_48_1","volume-title":"Lest we remember: cold-boot attacks on encryption keys,\" Communications of the ACM (CACM)","author":"Halderman J. A.","year":"2009","unstructured":"J. A. Halderman, S. D. Schoen, N. Heninger, W. Clarkson, W. Paul, J. A. Calandrino, A. J. Feldman, J. Appelbaum, and E. W. Felten, \"Lest we remember: cold-boot attacks on encryption keys,\" Communications of the ACM (CACM), 2009."},{"key":"e_1_3_2_1_49_1","volume-title":"TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks,\" in USENIX Security Symposium","author":"Rahmati A.","year":"2012","unstructured":"A. Rahmati, M. Salajegheh, D. Holcomb, J. Sorber, W. P. Burleson, and K. Fu, \"TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks,\" in USENIX Security Symposium, 2012."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4614-1460-5","volume-title":"Bootstrapping trust in modern computers","author":"Parno B.","year":"2011","unstructured":"B. Parno, J. M. McCune, and A. Perrig, Bootstrapping trust in modern computers. Springer Science & Business Media, 2011."},{"key":"e_1_3_2_1_51_1","volume-title":"The unpatchable silicon: A full break of the bitstream encryption of xilinx 7-series fpgas,\" in USENIX Security Symposium","author":"Ender M.","year":"2020","unstructured":"M. Ender, A. Moradi, and C. Paar, \"The unpatchable silicon: A full break of the bitstream encryption of xilinx 7-series fpgas,\" in USENIX Security Symposium, 2020."},{"key":"e_1_3_2_1_52_1","unstructured":"\"Arm Platform Security Architecture Security Model.\" https:\/\/armkeil.blob.core.windows.net\/developer\/Files\/pdf\/PlatformSecurityArchitecture\/Architect\/DEN0079-PSA_SM_ALPHA-02.pdf."},{"key":"e_1_3_2_1_53_1","unstructured":"\"PSA Attestation API.\" https:\/\/armkeil.blob.core.windows.net\/developer\/Files\/pdf\/PlatformSecurityArchitecture\/Implement\/IHI0085-PSA_Attestation_API-1.0.1-2.pdf."},{"key":"e_1_3_2_1_54_1","volume-title":"BOOMERANG: Exploiting the Semantic Gap in Trusted Execution Environments,\" in Network and Distributed System Security Symposium (NDSS)","author":"Machiry A.","year":"2017","unstructured":"A. Machiry, E. Gustafson, C. Spensky, C. Salls, N. Stephens, R. Wang, A. Bianchi, Y. R. Choe, C. Kruegel, and G. Vigna, \"BOOMERANG: Exploiting the Semantic Gap in Trusted Execution Environments,\" in Network and Distributed System Security Symposium (NDSS), 2017."},{"key":"e_1_3_2_1_55_1","first-page":"465","volume-title":"Design and verification of the arm confidential compute architecture,\" in 16th USENIX Symposium on Operating Systems Design and Implementation (OSDI 22)","author":"Li X.","year":"2022","unstructured":"X. Li, X. Li, C. Dall, R. Gu, J. Nieh, Y. Sait, and G. Stockwell, \"Design and verification of the arm confidential compute architecture,\" in 16th USENIX Symposium on Operating Systems Design and Implementation (OSDI 22), pp. 465--484, 2022."},{"key":"e_1_3_2_1_56_1","volume-title":"Ambassy: A Runtime Framework to Delegate Trusted Applications in an ARM\/FPGA Hybrid System,\" IEEE Transactions on Mobile Computing (TMC)","author":"Hwang D.","year":"2021","unstructured":"D. Hwang, S. Yeleuov, J. Seo, M. Chung, H. Moon, and Y. Paek, \"Ambassy: A Runtime Framework to Delegate Trusted Applications in an ARM\/FPGA Hybrid System,\" IEEE Transactions on Mobile Computing (TMC), 2021."},{"key":"e_1_3_2_1_57_1","volume-title":"FPGA-based remote power side-channel attacks,\" in IEEE symposium on Security and Privacy (S&P)","author":"Zhao M.","year":"2018","unstructured":"M. Zhao and G. E. Suh, \"FPGA-based remote power side-channel attacks,\" in IEEE symposium on Security and Privacy (S&P), 2018."},{"key":"e_1_3_2_1_58_1","unstructured":"Xilinx \"Xilinx Vivado Toolkit.\" https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html."},{"key":"e_1_3_2_1_59_1","unstructured":"Intel \"Intel Quartus Prime Pro Edition Design Software.\" https:\/\/www.intel.com\/content\/www\/us\/en\/software-kit\/706104\/intel-quartus-prime-pro-edition-design-software-version-21-4-for-linux.html?"},{"key":"e_1_3_2_1_60_1","volume-title":"DIAT: Data Integrity Attestation for Resilient Collaboration of Autonomous Systems.,\" in Network and Distributed System Security Symposium (NDSS)","author":"Abera T.","year":"2019","unstructured":"T. Abera, R. Bahmani, F. Brasser, A. Ibrahim, A.-R. Sadeghi, and M. Schunter, \"DIAT: Data Integrity Attestation for Resilient Collaboration of Autonomous Systems.,\" in Network and Distributed System Security Symposium (NDSS), 2019."},{"key":"e_1_3_2_1_61_1","volume-title":"Sgxio: Generic trusted i\/o path for intel sgx,\" in ACM on Conference on Data and Application Security and Privacy (CODASPY)","author":"Weiser S.","year":"2017","unstructured":"S. Weiser and M. Werner, \"Sgxio: Generic trusted i\/o path for intel sgx,\" in ACM on Conference on Data and Application Security and Privacy (CODASPY), 2017."},{"key":"e_1_3_2_1_62_1","unstructured":"Xilinx \"MicroBlaze.\" https:\/\/www.xilinx.com\/products\/design-tools\/microblaze.html 2018."},{"key":"e_1_3_2_1_63_1","unstructured":"Xilinx \"7 Series FPGAs Memory Resources..\" https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug473_7Series_Memory_Resources.pdf 2019."},{"key":"e_1_3_2_1_64_1","volume-title":"Leaky wires: Information leakage and covert communication between FPGA long wires,\" in Asia Conference on Computer and Communications Security (AsiaCCS)","author":"Giechaskiel I.","year":"2018","unstructured":"I. Giechaskiel, K. B. Rasmussen, and K. Eguro, \"Leaky wires: Information leakage and covert communication between FPGA long wires,\" in Asia Conference on Computer and Communications Security (AsiaCCS), 2018."},{"key":"e_1_3_2_1_65_1","volume-title":"FPGA side channel attacks without physical access,\" in Annual international symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Ramesh C.","year":"2018","unstructured":"C. Ramesh, S. B. Patil, S. N. Dhanuskodi, G. Provelengios, S. Pillement, D. Holcomb, and R. Tessier, \"FPGA side channel attacks without physical access,\" in Annual international symposium on Field-Programmable Custom Computing Machines (FCCM), 2018."},{"key":"e_1_3_2_1_66_1","volume-title":"Stereo Audio Input and Output.\" https:\/\/store.digilentinc.com\/pmod-i2s2-stereo-audio-input-and-output\/","author":"Pmod","year":"2018","unstructured":"\"Pmod I2S2: Stereo Audio Input and Output.\" https:\/\/store.digilentinc.com\/pmod-i2s2-stereo-audio-input-and-output\/, 2018."},{"key":"e_1_3_2_1_67_1","unstructured":"\"BLAKE2---fast secure hashing.\" https:\/\/www.blake2.net\/ 2015."},{"key":"e_1_3_2_1_68_1","unstructured":"\"Embench IoT benchmark Cortex-M4 data.\" https:\/\/gitlab.inria.fr\/mescoute\/embench-iot\/-\/tree\/76e887fac691d3d3f42cd32636b347bf2626036b\/doc."},{"key":"e_1_3_2_1_69_1","unstructured":"Linaro \"Trusted Firmware M (TFM) v1.3.0.\" https:\/\/git.trustedfirmware.org\/TF-M\/trusted-firmware-m.git."},{"key":"e_1_3_2_1_70_1","unstructured":"\"Gramine Project.\" https:\/\/github.com\/gramineproject\/gramine."},{"key":"e_1_3_2_1_71_1","unstructured":"\"Embench IoT.\" https:\/\/github.com\/embench\/embench-iot 2021."},{"key":"e_1_3_2_1_72_1","unstructured":"ARM \"Arm Cortex-M4 Processor Datasheet.\" https:\/\/developer.arm.com\/documentation\/102832 2020."},{"key":"e_1_3_2_1_73_1","volume-title":"Flicker: An execution infrastructure for TCB minimization,\" in European Conference on Computer Systems (EuroSys)","author":"McCune J. M.","year":"2008","unstructured":"J. M. McCune, B. J. Parno, A. Perrig, M. K. Reiter, and H. Isozaki, \"Flicker: An execution infrastructure for TCB minimization,\" in European Conference on Computer Systems (EuroSys), 2008."},{"key":"e_1_3_2_1_74_1","volume-title":"TrustVisor: Efficient TCB reduction and attestation,\" in IEEE symposium on Security and Privacy (S&P)","author":"McCune J. M.","year":"2010","unstructured":"J. M. McCune, Y. Li, N. Qu, Z. Zhou, A. Datta, V. Gligor, and A. Perrig, \"TrustVisor: Efficient TCB reduction and attestation,\" in IEEE symposium on Security and Privacy (S&P), 2010."},{"key":"e_1_3_2_1_75_1","volume-title":"Shielding Applications from an Untrusted Cloud with Haven,\" in USENIX symposium on Operating Systems Design and Implementation (OSDI)","author":"Baumann A.","year":"2014","unstructured":"A. Baumann, M. Peinado, and G. Hunt, \"Shielding Applications from an Untrusted Cloud with Haven,\" in USENIX symposium on Operating Systems Design and Implementation (OSDI), 2014."},{"key":"e_1_3_2_1_76_1","volume-title":"Sgx-fpga: Trusted execution environment for cpu-fpga heterogeneous architecture,\" in IEEE Design Automation Conference (DAC)","author":"Xia K.","year":"2021","unstructured":"K. Xia, Y. Luo, X. Xu, and S. Wei, \"Sgx-fpga: Trusted execution environment for cpu-fpga heterogeneous architecture,\" in IEEE Design Automation Conference (DAC), 2021."},{"key":"e_1_3_2_1_77_1","volume-title":"Keystone: An Open Framework for Architecting Trusted Execution Environments,\" in European Conference on Computer Systems (EuroSys)","author":"Lee D.","year":"2020","unstructured":"D. Lee, D. Kohlbrenner, S. Shinde, K. Asanovi\u0107, and D. Song, \"Keystone: An Open Framework for Architecting Trusted Execution Environments,\" in European Conference on Computer Systems (EuroSys), 2020."},{"key":"e_1_3_2_1_78_1","volume-title":"Sanctum: Minimal hardware extensions for strong software isolation,\" in USENIX Security Symposium","author":"Costan V.","year":"2016","unstructured":"V. Costan, I. Lebedev, and S. Devadas, \"Sanctum: Minimal hardware extensions for strong software isolation,\" in USENIX Security Symposium, 2016."},{"key":"e_1_3_2_1_79_1","volume-title":"Trustice: Hardware-assisted isolated computing environments on mobile devices,\" in Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN)","author":"Sun H.","year":"2015","unstructured":"H. Sun, K. Sun, Y. Wang, J. Jing, and H. Wang, \"Trustice: Hardware-assisted isolated computing environments on mobile devices,\" in Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN), 2015."},{"key":"e_1_3_2_1_80_1","volume-title":"vtz: Virtualizing ARM trustzone,\" in USENIX Security Symposium","author":"Hua Z.","year":"2017","unstructured":"Z. Hua, J. Gu, Y. Xia, H. Chen, B. Zang, and H. Guan, \"vtz: Virtualizing ARM trustzone,\" in USENIX Security Symposium, 2017."},{"key":"e_1_3_2_1_81_1","volume-title":"utango: an open-source tee for iot devices,\" IEEE Access","author":"Oliveira D.","year":"2022","unstructured":"D. Oliveira, T. Gomes, and S. Pinto, \"utango: an open-source tee for iot devices,\" IEEE Access, 2022."},{"key":"e_1_3_2_1_82_1","volume-title":"Strongbox: A gpu tee on arm endpoints,\" in Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security","author":"Deng Y.","year":"2022","unstructured":"Y. Deng, C. Wang, S. Yu, S. Liu, Z. Ning, K. Leach, J. Li, S. Yan, Z. He, J. Cao, et al., \"Strongbox: A gpu tee on arm endpoints,\" in Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022."},{"key":"e_1_3_2_1_83_1","volume-title":"Towards a Trusted Execution Environment via Reconfigurable FPGA,\" arXiv preprint arXiv:2107.03781","author":"Sergio Pereira C. R.","year":"2021","unstructured":"C. R. Sergio Pereira, David Cerdeira and S. Pinto, \"Towards a Trusted Execution Environment via Reconfigurable FPGA,\" arXiv preprint arXiv:2107.03781, 2021."},{"key":"e_1_3_2_1_84_1","volume-title":"Sancus: Low-cost trustworthy extensible networked devices with a zero-software trusted computing base,\" in 2USENIX Security Symposium","author":"Noorman J.","year":"2013","unstructured":"J. Noorman, P. Agten, W. Daniels, R. Strackx, A. Van Herrewege, C. Huygens, B. Preneel, I. Verbauwhede, and F. Piessens, \"Sancus: Low-cost trustworthy extensible networked devices with a zero-software trusted computing base,\" in 2USENIX Security Symposium, 2013."},{"key":"e_1_3_2_1_85_1","volume-title":"Secureblue++: Cpu support for secure execution,\" IBM Research Division","author":"Boivie R.","year":"2012","unstructured":"R. Boivie and P. Williams, \"Secureblue++: Cpu support for secure execution,\" IBM Research Division, 2012."},{"key":"e_1_3_2_1_86_1","volume-title":"Trustlite: A security architecture for tiny embedded devices,\" in European Conference on Computer Systems","author":"Koeberl P.","year":"2014","unstructured":"P. Koeberl, S. Schulz, A.-R. Sadeghi, and V. Varadharajan, \"Trustlite: A security architecture for tiny embedded devices,\" in European Conference on Computer Systems, 2014."},{"key":"e_1_3_2_1_87_1","volume-title":"Smart: secure and minimal architecture for (establishing dynamic) root of trust.,\" in Network and Distributed System Security Symposium (NDSS)","author":"Eldefrawy K.","year":"2012","unstructured":"K. Eldefrawy, G. Tsudik, A. Francillon, and D. Perito, \"Smart: secure and minimal architecture for (establishing dynamic) root of trust.,\" in Network and Distributed System Security Symposium (NDSS), 2012."},{"key":"e_1_3_2_1_88_1","unstructured":"S. Han and J. Jang \"Mytee: Own the trusted execution environment on embedded devices \""},{"key":"e_1_3_2_1_89_1","volume-title":"MeetGo: A Trusted Execution Environment for Remote Applications on FPGA,\" IEEE Access","author":"Oh H.","year":"2021","unstructured":"H. Oh, K. Nam, S. Jeon, Y. Cho, and Y. Paek, \"MeetGo: A Trusted Execution Environment for Remote Applications on FPGA,\" IEEE Access, 2021."},{"key":"e_1_3_2_1_90_1","volume-title":"Titan: enabling a transparent silicon root of trust for Cloud,\" in Hot Chips: A Symposium on High Performance Chips","author":"Johnson S.","year":"2018","unstructured":"S. Johnson, D. Rizzo, P. Ranganathan, J. McCune, and R. Ho, \"Titan: enabling a transparent silicon root of trust for Cloud,\" in Hot Chips: A Symposium on High Performance Chips, 2018."},{"key":"e_1_3_2_1_91_1","unstructured":"Samsung \"eSE Safeguard against digital attacks..\" https:\/\/www.samsung.com\/semiconductor\/security\/ese\/ 2020."},{"key":"e_1_3_2_1_92_1","unstructured":"Apple \"Security enclave processor for a system on a chip.\" https:\/\/patents.google.com\/patent\/US8832465 2020."},{"key":"e_1_3_2_1_93_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE)","author":"Vliegen J.","year":"2019","unstructured":"J. Vliegen, M. M. Rabbani, M. Conti, and N. Mentens, \"SACHa: Self-attestation of configurable hardware,\" in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019."},{"key":"e_1_3_2_1_94_1","volume-title":"On the TOCTOU problem in remote attestation,\" in ACM Conference on Computer and Communications Security","author":"Nunes I. De Oliveira","year":"2021","unstructured":"I. De Oliveira Nunes, S. Jakkamsetti, N. Rattanavipanon, and G. Tsudik, \"On the TOCTOU problem in remote attestation,\" in ACM Conference on Computer and Communications Security, 2021."},{"key":"e_1_3_2_1_95_1","author":"Kuon I.","year":"2007","unstructured":"I. Kuon and J. Rose, \"Measuring the gap between fpgas and asics,\" IEEE Transactions on computer-aided design of integrated circuits and systems, 2007.","journal-title":"\"Measuring the gap between fpgas and asics,\" IEEE Transactions on computer-aided design of integrated circuits and systems"},{"key":"e_1_3_2_1_96_1","unstructured":"Xilinx \"MicroBlaze Debug Modulev3.2.\" https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/mdm\/v3_2\/pg115-mdm.pdf 2021."},{"key":"e_1_3_2_1_97_1","unstructured":"Xilinx \"LogiCORE IP Product Guide.\" https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/axi_timer\/v2_0\/pg079-axi-timer.pdf 2016."},{"key":"e_1_3_2_1_98_1","unstructured":"Xilinx \"AXI GPIO v2.0.\" https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/axi_gpio\/v2_0\/pg144-axi-gpio.pdf 2016."},{"key":"e_1_3_2_1_99_1","unstructured":"Xilinx \"AXI DMA v7.1.\" https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/axi_dma\/v7_1\/pg021_axi_dma.pdf 2019."},{"key":"e_1_3_2_1_100_1","unstructured":"Xilinx \"AXI4-Stream FIFO v4.1.\" https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/axi_fifo_mm_s\/v4_1\/pg080-axi-fifo-mm-s.pdf 2016."},{"key":"e_1_3_2_1_101_1","unstructured":"Xilinx \"XADC Wizard v3.3.\" https:\/\/china.xilinx.com\/support\/documentation\/ip_documentation\/xadc_wiz\/v3_3\/pg091-xadc-wiz.pdf 2016."}],"event":{"name":"ASIA CCS '24: 19th ACM Asia Conference on Computer and Communications Security","location":"Singapore Singapore","acronym":"ASIA CCS '24","sponsor":["SIGSAC ACM Special Interest Group on Security, Audit, and Control"]},"container-title":["Proceedings of the 19th ACM Asia Conference on Computer and Communications Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3634737.3637644","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T23:44:05Z","timestamp":1750290245000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3634737.3637644"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7]]},"references-count":101,"alternative-id":["10.1145\/3634737.3637644","10.1145\/3634737"],"URL":"https:\/\/doi.org\/10.1145\/3634737.3637644","relation":{},"subject":[],"published":{"date-parts":[[2024,7]]},"assertion":[{"value":"2024-07-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}