{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,9]],"date-time":"2026-05-09T17:06:16Z","timestamp":1778346376962,"version":"3.51.4"},"reference-count":2,"publisher":"Association for Computing Machinery (ACM)","issue":"6","license":[{"start":{"date-parts":[[2023,12,31]],"date-time":"2023-12-31T00:00:00Z","timestamp":1703980800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Queue"],"published-print":{"date-parts":[[2023,12,31]]},"abstract":"<jats:p>Over the past decade I've been involved in several projects that have designed either ISA (instruction set architecture) extensions or clean-slate ISAs for various kinds of processors (you'll even find my name in the acknowledgments for the RISC-V spec, right back to the first public version). When I started, I had very little idea about what makes a good ISA, and, as far as I can tell, this isn't formally taught anywhere. With the rise of RISC-V as an open base for custom instruction sets, however, the barrier to entry has become much lower and the number of people trying to design some or all of an instruction set has grown immeasurably.<\/jats:p>","DOI":"10.1145\/3639445","type":"journal-article","created":{"date-parts":[[2024,1,12]],"date-time":"2024-01-12T03:04:47Z","timestamp":1705028687000},"page":"27-46","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["How to Design an ISA"],"prefix":"10.1145","volume":"21","author":[{"given":"David","family":"Chisnall","sequence":"first","affiliation":[{"name":"SCI Semiconductor"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,1,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Chisnall D. 2014. There's no such thing as a general-purpose processor. acmqueue 12(10); https:\/\/queue.acm.org\/detail.cfm?id=2687011.","DOI":"10.1145\/2685690.2687011"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Chow F. 2013. The challenge of cross-language interoperability. acmqueue 11(10); https:\/\/queue.acm.org\/detail.cfm?id=2544374.","DOI":"10.1145\/2542661.2543971"}],"container-title":["Queue"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3639445","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3639445","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:53:37Z","timestamp":1750287217000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3639445"}},"subtitle":["The popularity of RISC-V has led many to try designing instruction sets."],"short-title":[],"issued":{"date-parts":[[2023,12,31]]},"references-count":2,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2023,12,31]]}},"alternative-id":["10.1145\/3639445"],"URL":"https:\/\/doi.org\/10.1145\/3639445","relation":{},"ISSN":["1542-7730","1542-7749"],"issn-type":[{"value":"1542-7730","type":"print"},{"value":"1542-7749","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,12,31]]},"assertion":[{"value":"2024-01-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}