{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,3]],"date-time":"2026-08-03T15:55:56Z","timestamp":1785772556081,"version":"3.56.0"},"publisher-location":"New York, NY, USA","reference-count":37,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,10,25]],"date-time":"2023-10-25T00:00:00Z","timestamp":1698192000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,10,25]]},"DOI":"10.1145\/3639856.3639858","type":"proceedings-article","created":{"date-parts":[[2024,5,17]],"date-time":"2024-05-17T11:49:10Z","timestamp":1715946550000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Design-Space Exploration of Systolic Array for Edge Inferencing Applications"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9650-3731","authenticated-orcid":false,"given":"Prashanth","family":"H C","sequence":"first","affiliation":[{"name":"International Institute of Information Technology Bangalore, IN"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-4427-5956","authenticated-orcid":false,"given":"Yash Dharmesh","family":"Mogal","sequence":"additional","affiliation":[{"name":"International Institute of Information Technology Bangalore, IN"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2278-9148","authenticated-orcid":false,"given":"Madhav","family":"Rao","sequence":"additional","affiliation":[{"name":"International Institute of information Technology, Bangalore, IN"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,5,17]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Systimator: A Design Space Exploration Methodology for Systolic Array based CNNs Acceleration on the FPGA-based Edge Nodes. CoRR abs\/1901.04986","author":"Ahmad Hazoor","year":"2019","unstructured":"Hazoor Ahmad, Muhammad Tanvir, Muhammad Abdullah, Muhammad\u00a0Usama Javed, Rehan Hafiz, and Muhammad Shafique. 2019. Systimator: A Design Space Exploration Methodology for Systolic Array based CNNs Acceleration on the FPGA-based Edge Nodes. CoRR abs\/1901.04986 (2019). http:\/\/arxiv.org\/abs\/1901.04986"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/EMBC44109.2020.9176590"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED51717.2021.9424301"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3198036"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3060945"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021738"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180604"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3219455"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/OJEMB.2023.3257987"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2019.2953106"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3566052"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPR56361.2022.9956192"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1186\/s13636-023-00275-w"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2015.7178941"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.454"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-S54099.2022.00018"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3139904"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC51149.2021.00053"},{"key":"e_1_3_2_1_19_1","volume-title":"Sparse Matrix Proceedings","author":"Kung Hsiang\u00a0Tsung","year":"1979","unstructured":"Hsiang\u00a0Tsung Kung and Charles\u00a0E Leiserson. 1979. Systolic arrays (for VLSI). In Sparse Matrix Proceedings 1978, Vol.\u00a01. Society for industrial and applied mathematics Philadelphia, PA, USA, 256\u2013282."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00421"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP43922.2022.9746499"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSS.2021.3059318"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVT.2019.2899972"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2019.2915257"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","unstructured":"Motoi Omachi Yuya Fujita Shinji Watanabe and Tianzi Wang. 2022. Non-Autoregressive End-To-End Automatic Speech Recognition Incorporating Downstream Natural Language Processing. In ICASSP 2022 - 2022 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP). 6772\u20136776. https:\/\/doi.org\/10.1109\/ICASSP43922.2022.9746067","DOI":"10.1109\/ICASSP43922.2022.9746067"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2023.3251417"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC57363.2022.00043"},{"key":"e_1_3_2_1_28_1","unstructured":"Ananda Samajdar Yuhao Zhu Paul Whatmough Matthew Mattina and Tushar Krishna. 2019. SCALE-Sim: Systolic CNN Accelerator Simulator. arxiv:1811.02883\u00a0[cs.DC]"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2842761"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2023.3270562"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS47522.2019.9020404"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062207"},{"key":"e_1_3_2_1_33_1","volume-title":"Jun.","author":"Clifford\u00a0Young William Reginald","year":"2018","unstructured":"Reginald Clifford\u00a0Young William John\u00a0Gulland. Google LLC, U.K. Patent GB2557703A, Jun. 2018. Performing average pooling in hardware."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-11740-9_34"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2022.3219202"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967011"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/IECON43393.2020.9254452"}],"event":{"name":"AIMLSystems 2023: The Third International Conference on Artificial Intelligence and Machine Learning Systems","location":"Bangalore India","acronym":"AIMLSystems 2023"},"container-title":["Proceedings of the Third International Conference on AI-ML Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3639856.3639858","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3639856.3639858","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,8,3]],"date-time":"2026-08-03T15:22:04Z","timestamp":1785770524000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3639856.3639858"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,25]]},"references-count":37,"alternative-id":["10.1145\/3639856.3639858","10.1145\/3639856"],"URL":"https:\/\/doi.org\/10.1145\/3639856.3639858","relation":{},"subject":[],"published":{"date-parts":[[2023,10,25]]},"assertion":[{"value":"2024-05-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}