{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T13:40:05Z","timestamp":1755870005253,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,11,3]],"date-time":"2023-11-03T00:00:00Z","timestamp":1698969600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,11,3]]},"DOI":"10.1145\/3640115.3640127","type":"proceedings-article","created":{"date-parts":[[2024,3,26]],"date-time":"2024-03-26T12:10:58Z","timestamp":1711455058000},"page":"74-78","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Optimized Gate Sizing for Improved Performance and Power Efficiency in Adder Circuits"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-6316-5340","authenticated-orcid":false,"given":"Junyu","family":"Jiang","sequence":"first","affiliation":[{"name":"School of Information Science and Technology, Southwest Jiaotong University, China"}]}],"member":"320","published-online":{"date-parts":[[2024,3,26]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Research on Design of Nanoscale CMOS High-Speed Low-Power Adder","author":"Xihe Tian","year":"2010","unstructured":"Tian Xihe. Research on Design of Nanoscale CMOS High-Speed Low-Power Adder. Xidian University, 2010."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1631\/FITEE.2200077"},{"issue":"04","key":"e_1_3_2_1_3_1","first-page":"63","article-title":"Design of Parallel Adder Circuit Based on Single-Electron Transistor","volume":"36","author":"Fang Wang","year":"2020","unstructured":"Wang Fang, Ying Shijian, Kong Weiming. Design of Parallel Adder Circuit Based on Single-Electron Transistor. Bulletin of Science and Technology, 2020, 36(04): 63-66+112.","journal-title":"Bulletin of Science and Technology"},{"key":"e_1_3_2_1_4_1","first-page":"0307","article-title":"Design of Ternary Quantum Reversible Half Adder, Full Adder, and Parallel Adder Circuits. Journal of Quantum Electronics: 1-9 [2023-07-15]. http:\/\/kns.cnki.net\/kcms\/detail\/34.1163.","author":"Qimei Tang","year":"2022","unstructured":"Tang Qimei. Design of Ternary Quantum Reversible Half Adder, Full Adder, and Parallel Adder Circuits. Journal of Quantum Electronics: 1-9 [2023-07-15]. http:\/\/kns.cnki.net\/kcms\/detail\/34.1163.TN.20220307.1555.002.html","journal-title":"TN."},{"issue":"06","key":"e_1_3_2_1_5_1","first-page":"802","article-title":"Power-Delay Product Optimization of Hybrid Carry-","volume":"48","author":"Aihua Zhang","year":"2018","unstructured":"Zhang Aihua. Power-Delay Product Optimization of Hybrid Carry-In Algorithm for Adders. Microelectronics, 2018, 48(06): 802-805.","journal-title":"Algorithm for Adders. Microelectronics"},{"issue":"03","key":"e_1_3_2_1_6_1","first-page":"339","article-title":"Optimized Design of Carry-Ahead Adder[J]","volume":"47","author":"Hao Yuan","year":"2014","unstructured":"Yuan Hao, Tang Jian, Fang Yi. Optimized Design of Carry-Ahead Adder[J]. Communication Technology, 2014, 47(03): 339-342.","journal-title":"Communication Technology"},{"key":"e_1_3_2_1_7_1","volume-title":"Research on All-Optical Carry-Ahead Adder Based on Semiconductor Optical Amplifier","author":"Yao Liu","year":"2023","unstructured":"Liu Yao. Research on All-Optical Carry-Ahead Adder Based on Semiconductor Optical Amplifier. Taiyuan Normal University, 2023."},{"issue":"04","key":"e_1_3_2_1_8_1","first-page":"495","article-title":"Optimization of Block Allocation for Two-Level Carry-Skip Adders","volume":"2007","author":"Xiaoping Cui","unstructured":"Cui Xiaoping, Wang Chenghua. Optimization of Block Allocation for Two-Level Carry-Skip Adders. Journal of Beijing University of Aeronautics and Astronautics, 2007(04): 495-499.","journal-title":"Journal of Beijing University of Aeronautics and Astronautics"},{"key":"e_1_3_2_1_9_1","volume-title":"Design of Digital Filters Based on Carry-Save Adders. Heilongjiang Science and Technology Information","author":"Xia Zhao","year":"2012","unstructured":"Zhao Xia, Yang Qian. Design of Digital Filters Based on Carry-Save Adders. Heilongjiang Science and Technology Information, 2012(29): 30."},{"key":"e_1_3_2_1_10_1","volume-title":"Intelligent Architecture and Smart City","author":"Tsinghua University Integrated Circuit Institute Team Achieves Sub-1nm Gate-Length Transistor for the First Time.","year":"2022","unstructured":"Tsinghua University Integrated Circuit Institute Team Achieves Sub-1nm Gate-Length Transistor for the First Time. Intelligent Architecture and Smart City, 2022(04): 4."},{"key":"e_1_3_2_1_11_1","volume-title":"High Integration Rectangular Gate U-shaped Channel Bilateral Tunneling Field-Effect Transistor","author":"Baoxin Yang","year":"2022","unstructured":"Yang Baoxin. High Integration Rectangular Gate U-shaped Channel Bilateral Tunneling Field-Effect Transistor. Shenyang University of Technology, 2022."},{"key":"e_1_3_2_1_12_1","volume-title":"Research on Low Loss Power MOSFET Device Structure and Radiation Mechanism","author":"Ruidi Wang","year":"2023","unstructured":"Wang Ruidi. Research on Low Loss Power MOSFET Device Structure and Radiation Mechanism. University of Electronic Science and Technology of China, 2023."},{"key":"e_1_3_2_1_13_1","volume-title":"Research on High-Reliability Driving Technology for SiC MOSFET","author":"Yinghui Xu","year":"2021","unstructured":"Xu Yinghui. Research on High-Reliability Driving Technology for SiC MOSFET. Shandong University, 2021."},{"key":"e_1_3_2_1_14_1","volume-title":"Research and Application of Optimization Technology for Matched Filter Gate Units in Near-Threshold Regions for High Energy Efficiency","author":"Zhiqiang Hao","year":"2017","unstructured":"Hao Zhiqiang. Research and Application of Optimization Technology for Matched Filter Gate Units in Near-Threshold Regions for High Energy Efficiency. Southeast University, 2017."}],"event":{"name":"ICITEE 2023: 6th International Conference on Information Technologies and Electrical Engineering","acronym":"ICITEE 2023","location":"Changde, Hunan China"},"container-title":["Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3640115.3640127","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3640115.3640127","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T13:12:14Z","timestamp":1755868334000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3640115.3640127"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11,3]]},"references-count":14,"alternative-id":["10.1145\/3640115.3640127","10.1145\/3640115"],"URL":"https:\/\/doi.org\/10.1145\/3640115.3640127","relation":{},"subject":[],"published":{"date-parts":[[2023,11,3]]},"assertion":[{"value":"2024-03-26","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}