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Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2024,3,31]]},"abstract":"<jats:p>\n            Field Programmable Gate Array (FPGA) is a versatile and programmable hardware platform, which makes it a promising candidate for accelerating Deep Neural Networks (DNNs). However, FPGA\u2019s computing energy efficiency is low due to the domination of energy consumption by interconnect data movement. In this article, we propose an all-digital Compute-in-memory FPGA architecture for deep learning acceleration. Furthermore, we present a bit-serial computing circuit of the Digital CIM core for accelerating vector-matrix multiplication (VMM) operations. A Network-CIM-deployer (\n            <jats:italic>\n              <jats:bold>NCIMD<\/jats:bold>\n            <\/jats:italic>\n            ) is also developed to support automatic deployment and mapping of DNN networks.\n            <jats:italic>\n              <jats:bold>NCIMD<\/jats:bold>\n            <\/jats:italic>\n            provides a user-friendly API of DNN models in Caffe format. Meanwhile, we introduce a Weight-stationary dataflow and describe the method of mapping a single layer of the network to the CIM array in the architecture. We conduct experimental tests on the proposed FPGA architecture in the field of Deep Learning (DL), as well as in non-DL fields, using different architectural layouts and mapping strategies. We also compare the results with the conventional FPGA architecture. The experimental results show that compared to the conventional FPGA architecture, the energy efficiency can achieve a maximum speedup of 16.1\u00d7, while the latency can decrease up to 40% in our proposed CIM FPGA architecture.\n          <\/jats:p>","DOI":"10.1145\/3640469","type":"journal-article","created":{"date-parts":[[2024,1,15]],"date-time":"2024-01-15T11:34:12Z","timestamp":1705318452000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration"],"prefix":"10.1145","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-5749-0045","authenticated-orcid":false,"given":"Yonggen","family":"Li","sequence":"first","affiliation":[{"name":"Zhejiang University, Hangzhou, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-1756-9286","authenticated-orcid":false,"given":"Xin","family":"Li","sequence":"additional","affiliation":[{"name":"Zhejiang University, Hangzhou, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5431-609X","authenticated-orcid":false,"given":"Haibin","family":"Shen","sequence":"additional","affiliation":[{"name":"Zhejiang University, Hangzhou, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-0378-3370","authenticated-orcid":false,"given":"Jicong","family":"Fan","sequence":"additional","affiliation":[{"name":"China Electronics Technology Group Corporation 58th Research Institute, Wuxi, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-6242-4239","authenticated-orcid":false,"given":"Yanfeng","family":"Xu","sequence":"additional","affiliation":[{"name":"China Electronics Technology Group Corporation 58th Research Institute, Wuxi, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3722-9979","authenticated-orcid":false,"given":"Kejie","family":"Huang","sequence":"additional","affiliation":[{"name":"Zhejiang University, Hangzhou, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,2,12]]},"reference":[{"issue":"8","key":"e_1_3_1_2_2","first-page":"2521","article-title":"IMAC: In-memory multi-bit multiplication and accumulation in 6T SRAM array","volume":"67","author":"Ali Mustafa","year":"2020","unstructured":"Mustafa Ali, Akhilesh Jaiswal, Sangamesh Kodge, Amogh Agrawal, Indranil Chakraborty, and Kaushik Roy. 2020. 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