{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:01:22Z","timestamp":1750309282744,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,9,22]],"date-time":"2023-09-22T00:00:00Z","timestamp":1695340800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,9,22]]},"DOI":"10.1145\/3641584.3641716","type":"proceedings-article","created":{"date-parts":[[2024,6,14]],"date-time":"2024-06-14T22:44:43Z","timestamp":1718405083000},"page":"886-890","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Design of High Performance Dynamic DMA Based on Multidimensional Nesting Technology"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-4251-9233","authenticated-orcid":false,"given":"Xin","family":"Li","sequence":"first","affiliation":[{"name":"Xi'an University of Posts &amp; Telecommunications, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4150-2213","authenticated-orcid":false,"given":"Xiaofeng","family":"Yang","sequence":"additional","affiliation":[{"name":"Xi'an University of Posts &amp; Telecommunications, China"}]}],"member":"320","published-online":{"date-parts":[[2024,6,14]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.19339\/j.issn.1674-2583.2022.12.006"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.19514\/j.cnki.cn32-1628"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.19339\/j.issn.1674-2583.2021.08.005"},{"key":"e_1_3_2_1_4_1","volume-title":"Research on DMA access data consistency optimization and verification platform for multi-core DSP [D]","author":"Ming Liu","year":"2016","unstructured":"Liu Ming. Research on DMA access data consistency optimization and verification platform for multi-core DSP [D]. National University of Defense Technology, 2016."},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of the 21st Annual Conference of Computer Engineering and Technology and the 7th Microprocessor Technology Forum","author":"Meidi Zhang","year":"2017","unstructured":"Zhang Meidi, Ma Sheng, Lei Yuanwu.Design and Verification of DMA Interface Based on AXI Protocol[C]\/\/China Computer Society. Proceedings of the 21st Annual Conference of Computer Engineering and Technology and the 7th Microprocessor Technology Forum .Hunan Science and Technology Press, 2017:10."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.26935\/d.cnki.gbjgu.2021.000534"},{"key":"e_1_3_2_1_7_1","volume-title":"Design and implementation of Efficient Direct Memory Access (DMA) Controller in Multiprocessor SoC: IEEE","author":"SHIRUR YJM, SHARMA KM, A","year":"2018","unstructured":"SHIRUR YJM, SHARMA KM, A A. Design and implementation of Efficient Direct Memory Access (DMA) Controller in Multiprocessor SoC: IEEE, 2018."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.27157\/d.cnki.ghzku.2020.006304"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","unstructured":"F. Shanehsazzadeh and MS Sadri \"Area and performance evaluation of central DMA controller in Xilinx embedded FPGA designs \" 2017 Iranian Conference on Electrical Engineering (ICEE) 2017 pp. 546-550 doi: 10.1109\/IranianCEE .2017.7985100.","DOI":"10.1109\/IranianCEE"},{"key":"e_1_3_2_1_10_1","volume-title":"A Reconfigurable Multi-function DMA Controller for High-Performance Computing Systems: IEEE","author":"NGUYEN HK, DONG KP, TRAN","year":"2018","unstructured":"NGUYEN HK, DONG KP, TRAN X. A Reconfigurable Multi-function DMA Controller for High-Performance Computing Systems: IEEE, 2018."},{"key":"e_1_3_2_1_11_1","volume-title":"Design and Implementation of DMA High Speed Channel and Driver Based on AXI Bus[D]","author":"Qiong Zhuang","year":"2019","unstructured":"Zhuang Qiong. Design and Implementation of DMA High Speed Channel and Driver Based on AXI Bus[D].University of Electronic Science and Technology of China,2019."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.27135\/d.cnki.ghudu.2021.001070"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.27389\/d.cnki.gxadu.2021.000392"},{"key":"e_1_3_2_1_14_1","volume-title":"Development of a Generic and a Reconfigurable UVM-Based Verification Environment for SoC Buses: IEEE","author":"HUSSIEN A, MOHAMED S, SOLIMAN","year":"2019","unstructured":"HUSSIEN A, MOHAMED S, SOLIMAN M, Development of a Generic and a Reconfigurable UVM-Based Verification Environment for SoC Buses: IEEE, 2019."}],"event":{"name":"AIPR 2023: 2023 6th International Conference on Artificial Intelligence and Pattern Recognition","acronym":"AIPR 2023","location":"Xiamen China"},"container-title":["2023 6th International Conference on Artificial Intelligence and Pattern Recognition (AIPR)"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3641584.3641716","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3641584.3641716","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T00:03:11Z","timestamp":1750291391000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3641584.3641716"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,22]]},"references-count":14,"alternative-id":["10.1145\/3641584.3641716","10.1145\/3641584"],"URL":"https:\/\/doi.org\/10.1145\/3641584.3641716","relation":{},"subject":[],"published":{"date-parts":[[2023,9,22]]},"assertion":[{"value":"2024-06-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}