{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,9]],"date-time":"2026-02-09T23:45:16Z","timestamp":1770680716842,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":10,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,9,22]],"date-time":"2023-09-22T00:00:00Z","timestamp":1695340800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,9,22]]},"DOI":"10.1145\/3641584.3641801","type":"proceedings-article","created":{"date-parts":[[2024,6,14]],"date-time":"2024-06-14T22:44:43Z","timestamp":1718405083000},"page":"1440-1445","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Implementation of a continuous high-speed data acquisition system based on FPGA"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-0901-9038","authenticated-orcid":false,"given":"Zhifei","family":"Dong","sequence":"first","affiliation":[{"name":"Xi'an University of Posts &amp; Telecommunications, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-0093-6616","authenticated-orcid":false,"given":"Wei","family":"He","sequence":"additional","affiliation":[{"name":"Xi'an University of Posts &amp; Telecommunications, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-8034-8767","authenticated-orcid":false,"given":"Yuji","family":"Wang","sequence":"additional","affiliation":[{"name":"Xi'an University of Posts &amp; Telecommunications, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-5158-9687","authenticated-orcid":false,"given":"Jiangnan","family":"Liu","sequence":"additional","affiliation":[{"name":"Xi'an University of Posts &amp; Telecommunications, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9467-1304","authenticated-orcid":false,"given":"Kun","family":"He","sequence":"additional","affiliation":[{"name":"Xi'an University of Posts &amp; Telecommunications, China"}]}],"member":"320","published-online":{"date-parts":[[2024,6,14]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11235-018-00539-3"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","first-page":"87","DOI":"10.1016\/j.micpro.2016.11.006","article-title":"High speed FPGA-based data acquisition system[J]","volume":"49","author":"Khedkar A A","year":"2017","unstructured":"Khedkar A A, Khade R H. High speed FPGA-based data acquisition system[J]. Microprocessors and Microsystems, 2017, 49: 87-94.","journal-title":"Microprocessors and Microsystems"},{"key":"e_1_3_2_1_3_1","volume-title":"Design of PCIe-gigabit Ethernet high-speed data interaction system based on FPGA[C]\/\/2021 asia-pacific conference on communications technology and computer science (ACCTCS)","author":"Lanxu J.","year":"2021","unstructured":"J. Lanxu, Y. Xiaoping, W. Rikun, , Design of PCIe-gigabit Ethernet high-speed data interaction system based on FPGA[C]\/\/2021 asia-pacific conference on communications technology and computer science (ACCTCS), IEEE (2021) 138\u2013142."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"Shuangbao Shu \u00a0Le Wang \u00a0Dongmei Liu \u00a0Meiwen Chen \u00a0Yuzhong Zhang \u00a0Jiarong Luo \u00a0Feng Ji; A high-speed data acquisition system based on FPGA for tokamak.\u00a0Rev Sci Instrum\u00a01 October 2018; 89 (10): 10K120.\u00a0","DOI":"10.1063\/1.5035364"},{"key":"e_1_3_2_1_5_1","first-page":"20180858","article-title":"15","author":"Zhao Y.","year":"2018","unstructured":"Y. Zhao, X. Liu, J. Yang, A Resource and Timing Optimized PCIe DMA Architecture Using FPGA Internal Data Buffer [J], vol. 15, IEICE Electronics Express, 2018, 20180858.","journal-title":"IEICE Electronics Express"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","first-page":"105577","DOI":"10.1016\/j.mejo.2022.105577","article-title":"Optimization design of high-speed data acquisition system based on DMA double cache mechanism[J]","volume":"129","author":"Zhou","year":"2022","unstructured":"Zhou W, Yang S. Optimization design of high-speed data acquisition system based on DMA double cache mechanism[J]. Microelectronics Journal, 2022, 129: 105577.","journal-title":"Microelectronics Journal"},{"key":"e_1_3_2_1_7_1","first-page":"424","volume-title":"International Conference on Intelligent Transportation, Big Data & Smart City (ICITBS), IEEE","author":"Shi H.","year":"2019","unstructured":"H. Shi, S. Zhang, Dual-channel Image Acquisition System Based on FPGA[C]\/\/2019 International Conference on Intelligent Transportation, Big Data & Smart City (ICITBS), IEEE, 2019, pp. 421\u2013424."},{"issue":"3","key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","first-page":"80","DOI":"10.7763\/IJCTE.2020.V12.1268","article-title":"A Reconfigurable Model-Based Design for Rapid Prototyping on FPGA","volume":"12","author":"Hussain Pirzada Syed Jahanzeb","year":"2020","unstructured":"Syed Jahanzeb Hussain Pirzada, Abid Murtaza, Tongge Xu, and Liu Jianwei, \"A Reconfigurable Model-Based Design for Rapid Prototyping on FPGA,\" International Journal of Computer Theory and Engineering vol. 12, no. 3, pp. 80-84, 2020.","journal-title":"International Journal of Computer Theory and Engineering"},{"issue":"3","key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","first-page":"69","DOI":"10.7763\/IJCTE.2020.V12.1266","article-title":"Design of Ethernet-VLC Data Conversion System Based on FPGA","volume":"12","author":"Sun Guiling","year":"2020","unstructured":"Guiling Sun, Weijian Zhao, Ruobin Wang, and Xuanjie Li, \"Design of Ethernet-VLC Data Conversion System Based on FPGA,\" International Journal of Computer Theory and Engineering vol. 12, no. 3, pp. 69-73, 2020.","journal-title":"International Journal of Computer Theory and Engineering"},{"issue":"3","key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","first-page":"46","DOI":"10.7763\/IJCTE.2019.V11.1240","article-title":"Research on Digital Correlator Algorithm Based on FPGA","volume":"11","author":"Sun Guiling","year":"2019","unstructured":"[1] Guiling Sun, Jun Jia, Tianyu Geng, and Xudong Ye, \"Research on Digital Correlator Algorithm Based on FPGA,\" International Journal of Computer Theory and Engineering vol. 11, no. 3, pp. 46-50, 2019.","journal-title":"International Journal of Computer Theory and Engineering"}],"event":{"name":"AIPR 2023: 2023 6th International Conference on Artificial Intelligence and Pattern Recognition","location":"Xiamen China","acronym":"AIPR 2023"},"container-title":["2023 6th International Conference on Artificial Intelligence and Pattern Recognition (AIPR)"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3641584.3641801","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3641584.3641801","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T00:03:05Z","timestamp":1750291385000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3641584.3641801"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,22]]},"references-count":10,"alternative-id":["10.1145\/3641584.3641801","10.1145\/3641584"],"URL":"https:\/\/doi.org\/10.1145\/3641584.3641801","relation":{},"subject":[],"published":{"date-parts":[[2023,9,22]]},"assertion":[{"value":"2024-06-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}