{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:22:00Z","timestamp":1755998520492,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":10,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,1,18]],"date-time":"2024-01-18T00:00:00Z","timestamp":1705536000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,1,18]]},"DOI":"10.1145\/3642921.3642926","type":"proceedings-article","created":{"date-parts":[[2024,3,6]],"date-time":"2024-03-06T11:40:56Z","timestamp":1709725256000},"page":"22-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Integration of RISC-V Page Table Walk in gem5 SE Mode"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1660-3984","authenticated-orcid":false,"given":"Mirco","family":"Mannino","sequence":"first","affiliation":[{"name":"University of Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-5142-5715","authenticated-orcid":false,"given":"Yinting","family":"Huang","sequence":"additional","affiliation":[{"name":"Imperial College London, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4998-0092","authenticated-orcid":false,"given":"Biagio","family":"Peccerillo","sequence":"additional","affiliation":[{"name":"University of Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7572-6733","authenticated-orcid":false,"given":"Alessio","family":"Medaglini","sequence":"additional","affiliation":[{"name":"University of Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7975-3632","authenticated-orcid":false,"given":"Sandro","family":"Bartolini","sequence":"additional","affiliation":[{"name":"Univerisity of Siena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,3,6]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815970"},{"key":"e_1_3_2_1_2_1","volume-title":"The GAP benchmark suite. arXiv preprint arXiv:1508.03619","author":"Beamer Scott","year":"2015","unstructured":"Scott Beamer, Krste Asanovi\u0107, and David Patterson. 2015. The GAP benchmark suite. arXiv preprint arXiv:1508.03619 (2015)."},{"key":"e_1_3_2_1_3_1","volume-title":"The gem5 simulator. ACM SIGARCH computer architecture news 39, 2","author":"Nathan Binkert","year":"2011","unstructured":"Nathan Binkert 2011. The gem5 simulator. ACM SIGARCH computer architecture news 39, 2 (2011), 1\u20137."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"Mirco\u00a0Mannino et al.2023. Integration of RISC-V Page Table Walk in gem5 SE Mode - Github Repository. https:\/\/github.com\/mircomannino\/gem5\/tree\/rapido24","DOI":"10.1145\/3642921.3642926"},{"key":"e_1_3_2_1_5_1","unstructured":"gem5 GitHub\u00a0repository. 2023. issue n. 484. https:\/\/github.com\/gem5\/gem5\/issues\/484"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2749471"},{"key":"e_1_3_2_1_7_1","volume-title":"The gem5 simulator: Version 20.0+. arXiv preprint arXiv:2007.03152","author":"Lowe-Power Jason","year":"2020","unstructured":"Jason Lowe-Power, Abdul\u00a0Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adri\u00e0 Armejach, Nils Asmussen, Brad Beckmann, Srikant Bharadwaj, 2020. The gem5 simulator: Version 20.0+. arXiv preprint arXiv:2007.03152 (2020)."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3587135.3592208"},{"volume-title":"Operating system concepts","author":"Peterson L","key":"e_1_3_2_1_9_1","unstructured":"James\u00a0L Peterson and Abraham Silberschatz. 1985. Operating system concepts. Addison-Wesley Longman Publishing Co., Inc."},{"key":"e_1_3_2_1_10_1","volume-title":"Privileged architecture version 1.7. EECS Department","author":"Waterman Andrew","year":"2015","unstructured":"Andrew Waterman, Yunsup Lee, Rimas Avizienis, David\u00a0A Patterson, and Krste Asanovic. 2015. The RISC-V instruction set manual volume II: Privileged architecture version 1.7. EECS Department, University of California, Berkeley, Tech. Rep. UCB\/EECS-2015-49 (2015)."}],"event":{"name":"RAPIDO '24: Rapid Simulation and Performance Evaluation for Design","acronym":"RAPIDO '24","location":"Munich Germany"},"container-title":["Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3642921.3642926","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3642921.3642926","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T20:24:17Z","timestamp":1755980657000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3642921.3642926"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1,18]]},"references-count":10,"alternative-id":["10.1145\/3642921.3642926","10.1145\/3642921"],"URL":"https:\/\/doi.org\/10.1145\/3642921.3642926","relation":{},"subject":[],"published":{"date-parts":[[2024,1,18]]},"assertion":[{"value":"2024-03-06","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}