{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,20]],"date-time":"2026-01-20T00:33:01Z","timestamp":1768869181001,"version":"3.49.0"},"reference-count":88,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2024,3,14]],"date-time":"2024-03-14T00:00:00Z","timestamp":1710374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Key R&D Project","award":["2021YFB0300300"],"award-info":[{"award-number":["2021YFB0300300"]}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"crossref","award":["62172430, 61872374, 62172155, and U22A2027"],"award-info":[{"award-number":["62172430, 61872374, 62172155, and U22A2027"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"NSF of Hunan Province","award":["2022JJ10064"],"award-info":[{"award-number":["2022JJ10064"]}]},{"name":"STIP of Hunan Province","award":["2022RC3065"],"award-info":[{"award-number":["2022RC3065"]}]},{"name":"Foundation of PDL","award":["2023-JKWPDL-02"],"award-info":[{"award-number":["2023-JKWPDL-02"]}]},{"name":"Key Laboratory of Advanced Microprocessor Chips and Systems, and NKRDP","award":["2023YFB4502100"],"award-info":[{"award-number":["2023YFB4502100"]}]},{"name":"Hunan Postgraduate Research Innovation Project","award":["CX20220077"],"award-info":[{"award-number":["CX20220077"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2024,5,31]]},"abstract":"<jats:p>Artificial neural networks (ANNs) and spiking neural networks (SNNs) are two general approaches to achieve artificial intelligence (AI). The former have been widely used in academia and industry fields; the latter, SNNs, are more similar to biological neural networks and can realize ultra-low power consumption, thus have received widespread research attention. However, due to their fundamental differences in computation formula and information coding, the two methods often require different and incompatible platforms. Alongside the development of AI, a general platform that can support both ANNs and SNNs is necessary. Moreover, there are some similarities between ANNs and SNNs, which leaves room to deploy different networks on the same architecture. However, there is little related research on this topic. Accordingly, this article presents an energy-efficient, scalable, and non-Von Neumann architecture (EPHA) for ANNs and SNNs. Our study combines device-, circuit-, architecture-, and algorithm-level innovations to achieve a parallel architecture with ultra-low power consumption. We use the compensated ferrimagnet to act as both synapses and neurons to store weights and perform dot-product operations, respectively. Moreover, we propose a novel computing flow to reduce the operations across multiple crossbar arrays, which enables our design to conduct large and complex tasks. On a suite of ANN and SNN workloads, the EPHA is 1.6\u00d7 more power-efficient than a state-of-the-art design, NEBULA, in the ANN mode. In the SNN mode, our design is 4 orders of magnitude more than the Loihi in power efficiency.<\/jats:p>","DOI":"10.1145\/3643134","type":"journal-article","created":{"date-parts":[[2024,1,25]],"date-time":"2024-01-25T12:38:57Z","timestamp":1706186337000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs"],"prefix":"10.1145","volume":"29","author":[{"given":"Yunping","family":"Zhao","sequence":"first","affiliation":[{"name":"Institute of Microelectronics and Microprocessors, College of Computer Science,National University of Defense Technology, Changsha, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1710-4060","authenticated-orcid":false,"given":"Sheng","family":"Ma","sequence":"additional","affiliation":[{"name":"National Key Laboratory of Parallel and Distributed Computing, College of Computer Science, National University of Defense Technology, Changsha, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4912-0364","authenticated-orcid":false,"given":"Hengzhu","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics and Microprocessors, College of Computer Science, National University of Defense Technology, Changsha, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7878-3998","authenticated-orcid":false,"given":"Libo","family":"Huang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics and Microprocessors, College of Computer Science, National University of Defense Technology, Changsha, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,3,14]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2313565"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1080\/23746149.2016.1259585"},{"issue":"1","key":"e_1_3_1_4_2","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1038\/s41928-019-0345-8","article-title":"Ultrafast and energy-efficient spin\u2013orbit torque switching in compensated ferrimagnets","volume":"3","author":"Cai Kaiming","year":"2020","unstructured":"Kaiming Cai, Zhifeng Zhu, Jong Min Lee, Rahul Mishra, Lizhu Ren, Shawn D. Pollard, Pan He, Gengchiau Liang, Kie Leong Teo, and Hyunsoo Yang. 2020. Ultrafast and energy-efficient spin\u2013orbit torque switching in compensated ferrimagnets. Nat. Electron. 3, 1 (2020), 37\u201342.","journal-title":"Nat. Electron."},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-014-0788-3"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-014-0788-3"},{"issue":"25","key":"e_1_3_1_7_2","doi-asserted-by":"crossref","first-page":"1808104","DOI":"10.1002\/adfm.201808104","article-title":"Tuning a binary ferromagnet into a multistate synapse with spin\u2013orbit-torque-induced plasticity","volume":"29","author":"Cao Yi","year":"2019","unstructured":"Yi Cao, Andrew W. Rushforth, Yu Sheng, Houzhi Zheng, and Kaiyou Wang. 2019. Tuning a binary ferromagnet into a multistate synapse with spin\u2013orbit-torque-induced plasticity. Adv. Functional Mater. 29, 25 (2019), 1808104.","journal-title":"Adv. Functional Mater."},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2884901"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2016.2598742"},{"key":"e_1_3_1_10_2","first-page":"C264\u2013C265","volume-title":"Symposium on VLSI Circuits","author":"Chen Vanessa H.-C.","year":"2013","unstructured":"Vanessa H.-C. Chen and Lawrence Pileggi. 2013. An 8.5 mW 5GS\/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI. In Symposium on VLSI Circuits. IEEE, C264\u2013C265."},{"key":"e_1_3_1_11_2","doi-asserted-by":"crossref","first-page":"609","DOI":"10.1109\/MICRO.2014.58","volume-title":"47th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Chen Yunji","year":"2014","unstructured":"Yunji Chen, Tao Luo, Shaoli Liu, Shijin Zhang, Liqiang He, Jia Wang, Ling Li, Tianshi Chen, Zhiwei Xu, Ninghui Sun, and Olivier Temam. 2014. DaDianNao: A machine-learning supercomputer. In 47th Annual IEEE\/ACM International Symposium on Microarchitecture. 609\u2013622."},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"e_1_3_1_13_2","first-page":"185","volume-title":"IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH\u201916)","author":"Cheng Hsin-Pai","year":"2016","unstructured":"Hsin-Pai Cheng, Wei Wen, Chang Song, Beiye Liu, Hai Li, and Yiran Chen. 2016. Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss. In IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH\u201916). IEEE, 185\u2013190."},{"key":"e_1_3_1_14_2","unstructured":"Mike Davies. 2021. Taking neuromorphic computing with Loihi 2 to the next level technology brief. https:\/\/download.intel.com\/newsroom\/2021\/new-technologies\/neuromorphic-computing-loihi-2-brief.pdf"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.112130359"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2012.2211477"},{"key":"e_1_3_1_18_2","first-page":"1","volume-title":"International Joint Conference on Neural Networks (IJCNN\u201915)","author":"Diehl Peter U.","year":"2015","unstructured":"Peter U. Diehl, Daniel Neil, Jonathan Binas, Matthew Cook, Shih-Chii Liu, and Michael Pfeiffer. 2015. Fast-classifying, high-accuracy spiking deep networks through weight and threshold balancing. In International Joint Conference on Neural Networks (IJCNN\u201915). IEEE, 1\u20138."},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2304638"},{"key":"e_1_3_1_20_2","article-title":"DCT-SNN: Using DCT to distribute spatial information over time for learning low-latency spiking neural networks","volume":"2010","author":"Garg Isha","year":"2020","unstructured":"Isha Garg, Sayeed Shafayet Chowdhury, and Kaushik Roy. 2020. DCT-SNN: Using DCT to distribute spatial information over time for learning low-latency spiking neural networks. CoRR abs\/2010.01795 (2020).","journal-title":"CoRR"},{"issue":"11","key":"e_1_3_1_21_2","first-page":"3207","article-title":"E3NE: An end-to-end framework for accelerating spiking neural networks with emerging neural encoding on fpgas","volume":"33","author":"Gerlinghoff Daniel","year":"2021","unstructured":"Daniel Gerlinghoff, Zhehui Wang, Xiaozhe Gu, Rick Siow Mong Goh, and Tao Luo. 2021. E3NE: An end-to-end framework for accelerating spiking neural networks with emerging neural encoding on fpgas. IEEE Trans. Parallel Distrib. Syst. 33, 11 (2021), 3207\u20133219.","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"e_1_3_1_22_2","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1145\/3352460.3358291","volume-title":"52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201952)","author":"Gondimalla Ashish","year":"2019","unstructured":"Ashish Gondimalla, Noah Chesnut, Mithuna Thottethodi, and T. N. Vijaykumar. 2019. SparTen: A sparse tensor accelerator for convolutional neural networks. In 52nd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201952). Association for Computing Machinery, New York, NY, 151\u2013165."},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.053631137"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.26599\/TST.2019.9010019"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.neuron.2017.06.011"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2015.2457393"},{"issue":"2","key":"e_1_3_1_28_2","doi-asserted-by":"crossref","first-page":"333","DOI":"10.1109\/TCDS.2021.3069871","article-title":"The why, what, and how of artificial general intelligence chip development","volume":"14","author":"James Alex P.","year":"2021","unstructured":"Alex P. James. 2021. The why, what, and how of artificial general intelligence chip development. IEEE Trans. Cognit. Develop. Syst. 14, 2 (2021), 333\u2013347.","journal-title":"IEEE Trans. Cognit. Develop. Syst."},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.ins.2014.06.028"},{"key":"e_1_3_1_30_2","first-page":"1","volume-title":"Symposium on VLSI Circuits","year":"2021","unstructured":"Riduan Khaddam-Aljameh, Milos Stanisavljevic, J. Fornt Mas, Geethan Karunaratne, Matthias Braendli, Femg Liu, Abhairaj Singh, Silvia M. M\u00fcller, Urs Egger, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Fee Li Lie, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, and Evangelos Eleftheriou. 2021. HERMES core\u2013A 14nm CMOS and PCM-based in-memory compute core using an array of 300ps\/LSB Linearized CCO-based ADCs and local digital processing. In Symposium on VLSI Circuits. IEEE, 1\u20132."},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1017\/S0140525X16001837"},{"issue":"6","key":"e_1_3_1_32_2","doi-asserted-by":"crossref","first-page":"2000182","DOI":"10.1002\/aisy.202000182","article-title":"Gradient descent on multilevel spin\u2014Orbit synapses with tunable variations","volume":"3","author":"Lan Xiukai","year":"2021","unstructured":"Xiukai Lan, Yi Cao, Xiangyu Liu, Kaijia Xu, Chuan Liu, Houzhi Zheng, and Kaiyou Wang. 2021. Gradient descent on multilevel spin\u2014Orbit synapses with tunable variations. Advanc. Intell. Syst. 3, 6 (2021), 2000182.","journal-title":"Advanc. Intell. Syst."},{"key":"e_1_3_1_33_2","first-page":"317","volume-title":"IEEE International Symposium on High-Performance Computer Architecture (HPCA\u201922)","author":"Lee Jeong-Jun","year":"2022","unstructured":"Jeong-Jun Lee, Wenrui Zhang, and Peng Li. 2022. Parallel time batching: Systolic-array acceleration of sparse spiking neural computation. In IEEE International Symposium on High-Performance Computer Architecture (HPCA\u201922). 317\u2013330."},{"key":"e_1_3_1_34_2","first-page":"71","volume-title":"Symposium on VLSI Technology (VLSIT\u201912)","author":"Lee Seung Ryul","year":"2012","unstructured":"Seung Ryul Lee, Young-Bae Kim, Man Chang, Kyung Min Kim, Chang Bum Lee, Ji Hyun Hur, Gyeong-Su Park, Dongsoo Lee, Myoung-Jae Lee, Chang Jung Kim, U-In Chung, In-Kyeong Yoo, and Kinam Kim. 2012. Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory. In Symposium on VLSI Technology (VLSIT\u201912). 71\u201372."},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11704-022-1322-3"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2017.00309"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2062187"},{"key":"e_1_3_1_38_2","first-page":"1","volume-title":"52nd ACM\/EDAC\/IEEE Design Automation Conference (DAC\u201915)","author":"Liu Beiye","year":"2015","unstructured":"Beiye Liu, Hai Li, Yiran Chen, Xin Li, Qing Wu, and Tingwen Huang. 2015. Vortex: Variation-aware training for memristor X-bar. In 52nd ACM\/EDAC\/IEEE Design Automation Conference (DAC\u201915). 1\u20136."},{"key":"e_1_3_1_39_2","first-page":"1692","volume-title":"AAAI Conference on Artificial Intelligence","author":"Liu Fangxin","year":"2022","unstructured":"Fangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, and Li Jiang. 2022. SpikeConverter: An efficient conversion framework zipping the gap between artificial neural networks and spiking neural networks. In AAAI Conference on Artificial Intelligence. 1692\u20131701."},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2021.756876"},{"key":"e_1_3_1_41_2","first-page":"1105","volume-title":"59th ACM\/IEEE Design Automation Conference (DAC\u201922)","author":"Liu Fangxin","year":"2022","unstructured":"Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Tao Yang, Zhezhi He, Xiaokang Yang, and Li Jiang. 2022. SATO: Spiking neural network acceleration via temporal-oriented dataflow and architecture. In 59th ACM\/IEEE Design Automation Conference (DAC\u201922). Association for Computing Machinery, New York, NY, 1105\u20131110."},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1002\/adfm.202107870"},{"issue":"1","key":"e_1_3_1_43_2","doi-asserted-by":"crossref","first-page":"014059","DOI":"10.1103\/PhysRevApplied.13.014059","article-title":"Tuning interfacial spins in antiferromagnetic\u2013ferromagnetic\u2013heavy-metal heterostructures via spin-orbit torque","volume":"13","author":"Liu X. H.","year":"2020","unstructured":"X. H. Liu, K. W. Edmonds, Z. P. Zhou, and K. Y. Wang. 2020. Tuning interfacial spins in antiferromagnetic\u2013ferromagnetic\u2013heavy-metal heterostructures via spin-orbit torque. Phys. Rev. Appl. 13, 1 (2020), 014059.","journal-title":"Phys. Rev. Appl."},{"key":"e_1_3_1_44_2","first-page":"122","volume-title":"Computer Vision (ECCV\u201918)","author":"Ma Ningning","year":"2018","unstructured":"Ningning Ma, Xiangyu Zhang, Hai-Tao Zheng, and Jian Sun. 2018. ShuffleNet V2: Practical guidelines for efficient CNN architecture design. In Computer Vision (ECCV\u201918). 122\u2013138."},{"key":"e_1_3_1_45_2","article-title":"SpiNNaker 2: A 10 million core processor system for brain simulation and machine learning","volume":"1911","author":"Mayr Christian","year":"2019","unstructured":"Christian Mayr, Sebastian H\u00f6ppner, and Steve B. Furber. 2019. SpiNNaker 2: A 10 million core processor system for brain simulation and machine learning. CoRR abs\/1911.02385 (2019).","journal-title":"CoRR"},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1126\/science.1254642"},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.physleta.2022.128024"},{"key":"e_1_3_1_48_2","first-page":"175","volume-title":"IEEE Symposium on VLSI Technology","author":"Mochida Reiji","year":"2018","unstructured":"Reiji Mochida, Kazuyuki Kouno, Yuriko Hayata, Masayoshi Nakayama, Takashi Ono, Hitoshi Suwa, Ryutaro Yasuhara, Koji Katayama, Takumi Mikawa, and Yasushi Gohou. 2018. A 4M synapses integrated analog ReRAM based 66.5 TOPS\/W neural-network processor with cell current controlled writing and flexible network architecture. In IEEE Symposium on VLSI Technology. IEEE, 175\u2013176."},{"key":"e_1_3_1_49_2","unstructured":"Boris Murmann. 2021. ADC performance survey 1997\u20132021. [Online]. Available: https:\/\/github.com\/bmurmann\/ADC-survey"},{"issue":"1","key":"e_1_3_1_50_2","first-page":"ii\u2013iii","article-title":"IEEE journal on exploratory solid-state computational devices and circuits","volume":"5","author":"Naeemi Azad","year":"2019","unstructured":"Azad Naeemi. 2019. IEEE journal on exploratory solid-state computational devices and circuits. IEEE J. Explorat. Solid-state Computat. Devices Circ. 5, 1 (2019), ii\u2013iii.","journal-title":"IEEE J. Explorat. Solid-state Computat. Devices Circ."},{"key":"e_1_3_1_51_2","first-page":"349","volume-title":"ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920)","author":"Narayanan Surya","year":"2020","unstructured":"Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, and Pierre-Emmanuel Gaillardon. 2020. SpinalFlow: An architecture and dataflow tailored for spiking neural networks. In ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920). 349\u2013362."},{"key":"e_1_3_1_52_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2013.2252317"},{"key":"e_1_3_1_53_2","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2015.2418033"},{"key":"e_1_3_1_54_2","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2019.2956112"},{"key":"e_1_3_1_55_2","first-page":"675","volume-title":"IEEE Biomedical Circuits and Systems Conference (BioCAS\u201914)","author":"Park Jongkil","year":"2014","unstructured":"Jongkil Park, Sohmyung Ha, Theodore Yu, Emre Neftci, and Gert Cauwenberghs. 2014. A 65k-neuron 73-Mevents\/s 22-pJ\/event asynchronous micro-pipelined integrate-and-fire array transceiver. In IEEE Biomedical Circuits and Systems Conference (BioCAS\u201914). IEEE, 675\u2013678."},{"key":"e_1_3_1_56_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-019-1424-8"},{"key":"e_1_3_1_57_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2958568"},{"issue":"2","key":"e_1_3_1_58_2","doi-asserted-by":"crossref","first-page":"357","DOI":"10.1109\/JPROC.2019.2948775","article-title":"The security of autonomous driving: Threats, defenses, and future directions","volume":"108","author":"Ren Kui","year":"2019","unstructured":"Kui Ren, Qian Wang, Cong Wang, Zhan Qin, and Xiaodong Lin. 2019. The security of autonomous driving: Threats, defenses, and future directions. Proc. IEEE 108, 2 (2019), 357\u2013372.","journal-title":"Proc. IEEE"},{"key":"e_1_3_1_59_2","first-page":"1","volume-title":"IEEE High Performance Extreme Computing Conference (HPEC\u201921)","author":"Reuther Albert","year":"2021","unstructured":"Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, and Jeremy Kepner. 2021. AI accelerator survey and trends. In IEEE High Performance Extreme Computing Conference (HPEC\u201921). IEEE, 1\u20139."},{"key":"e_1_3_1_60_2","doi-asserted-by":"publisher","DOI":"10.1145\/3465371"},{"key":"e_1_3_1_61_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2107214"},{"key":"e_1_3_1_62_2","first-page":"4557","volume-title":"International Joint Conference on Neural Networks (IJCNN\u201917)","author":"Sengupta Abhronil","year":"2017","unstructured":"Abhronil Sengupta, Aayush Ankit, and Kaushik Roy. 2017. Performance analysis and benchmarking of all-spin spiking neural networks (special session paper). In International Joint Conference on Neural Networks (IJCNN\u201917). IEEE, 4557\u20134563."},{"key":"e_1_3_1_63_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2615312"},{"key":"e_1_3_1_64_2","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2016.2525823"},{"issue":"3","key":"e_1_3_1_65_2","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1145\/3007787.3001139","article-title":"ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars","volume":"44","author":"Shafiee Ali","year":"2016","unstructured":"Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, and Vivek Srikumar. 2016. ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. ACM SIGARCH Comput. Archit. News 44, 3 (2016), 14\u201326.","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"e_1_3_1_66_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586323"},{"key":"e_1_3_1_67_2","article-title":"Very deep convolutional networks for large-scale image recognition","author":"Simonyan Karen","year":"2014","unstructured":"Karen Simonyan and Andrew Zisserman. 2014. Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556.","journal-title":"arXiv preprint arXiv:1409.1556"},{"key":"e_1_3_1_68_2","first-page":"363","volume-title":"ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920)","author":"Singh Sonali","year":"2020","unstructured":"Sonali Singh, Anup Sarma, Nicholas Jao, Ashutosh Pattnaik, Sen Lu, Kezhou Yang, Abhronil Sengupta, Vijaykrishnan Narayanan, and Chita R. Das. 2020. NEBULA: A neuromorphic spin-based ultra-low power architecture for SNNs and ANNs. In ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920). IEEE, 363\u2013376."},{"key":"e_1_3_1_69_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11704-021-0353-5"},{"key":"e_1_3_1_70_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.308"},{"issue":"7805","key":"e_1_3_1_71_2","doi-asserted-by":"crossref","first-page":"608","DOI":"10.1038\/s41586-020-2211-2","article-title":"Electrical manipulation of a topological antiferromagnetic state","volume":"580","year":"2020","unstructured":"Hanshen Tsai, Tomoya Higo, Kouta Kondou, Takuya Nomoto, Akito Sakai, Ayuko Kobayashi, Takafumi Nakano, Kay Yakushiji, Ryotaro Arita, Shinji Miwa,Yoshichika Otani, and Satoru Nakatsuji. 2020. Electrical manipulation of a topological antiferromagnetic state. Nature 580, 7805 (2020), 608\u2013613.","journal-title":"Nature"},{"issue":"6428","key":"e_1_3_1_72_2","doi-asserted-by":"crossref","first-page":"692","DOI":"10.1126\/science.aau6595","article-title":"Using neuroscience to develop artificial intelligence","volume":"363","author":"Ullman Shimon","year":"2019","unstructured":"Shimon Ullman. 2019. Using neuroscience to develop artificial intelligence. Science 363, 6428 (2019), 692\u2013693.","journal-title":"Science"},{"key":"e_1_3_1_73_2","doi-asserted-by":"publisher","DOI":"10.1063\/1.4899186"},{"key":"e_1_3_1_74_2","doi-asserted-by":"crossref","unstructured":"Abhay S. Vidhyadharan Gangavarapu Anuhya Shivangi Shukla and Sanjay Vidhyadharan. 2023. Fast and low-power CMOS and CNFET based hysteresis voltage comparator. IETE Journal of Research (2023) 1\u201312.","DOI":"10.1080\/03772063.2023.2165176"},{"key":"e_1_3_1_75_2","article-title":"A survey of design and optimization for systolic array based DNN accelerators","author":"Xu Rui","year":"2023","unstructured":"Rui Xu, Sheng Ma, Yang Guo, and Dongsheng Li. 2023. A survey of design and optimization for systolic array based DNN accelerators. Comput. Surv. (2023).","journal-title":"Comput. Surv."},{"issue":"4","key":"e_1_3_1_76_2","first-page":"42","article-title":"Configurable multi-directional systolic array architecture for convolutional neural networks","volume":"18","author":"Xu Rui","year":"2021","unstructured":"Rui Xu, Sheng Ma, Yaohua Wang, Xinhai Chen, and Yang Guo. 2021. Configurable multi-directional systolic array architecture for convolutional neural networks. ACM Trans. Archit. Code Optim. 18, 4, Article 42 (July2021), 24 pages.","journal-title":"ACM Trans. Archit. Code Optim."},{"issue":"11","key":"e_1_3_1_77_2","first-page":"2860","article-title":"Heterogeneous systolic array architecture for compact CNNS hardware accelerators","volume":"33","author":"Xu Rui","year":"2022","unstructured":"Rui Xu, Sheng Ma, Yaohua Wang, Yang Guo, Dongsheng Li, and Yuran Qiao. 2022. Heterogeneous systolic array architecture for compact CNNS hardware accelerators. IEEE Trans. Parallel Distrib. Syst. 33, 11 (2022), 2860\u20132871.","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"e_1_3_1_78_2","first-page":"388","volume-title":"IEEE International Solid-State Circuits Conference (ISSCC\u201919)","year":"2019","unstructured":"Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, Chung-Chuan Lo, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, and Meng-Fan Chang. 2019. 24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors. In IEEE International Solid-State Circuits Conference (ISSCC\u201919). IEEE, 388\u2013390."},{"issue":"1","key":"e_1_3_1_79_2","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1038\/s41427-021-00282-3","article-title":"Integrated neuromorphic computing networks by artificial spin synapses and spin neurons","volume":"13","year":"2021","unstructured":"Seungmo Yang, Jeonghun Shin, Taeyoon Kim, Kyoung-Woong Moon, Jaewook Kim, Gabriel Jang, Da Seul Hyeon, Jungyup Yang, Chanyong Hwang, YeonJoo Jeong, and JinPyo Hong. 2021. Integrated neuromorphic computing networks by artificial spin synapses and spin neurons. NPG Asia Mater. 13, 1 (2021), 11.","journal-title":"NPG Asia Mater."},{"key":"e_1_3_1_80_2","doi-asserted-by":"crossref","first-page":"1916","DOI":"10.1109\/ACSSC.2017.8335698","volume-title":"51st Asilomar Conference on Signals, Systems, and Computers","author":"Yang Tien-Ju","year":"2017","unstructured":"Tien-Ju Yang, Yu-Hsin Chen, and Joel Emer. 2017. A method to estimate the energy consumption of deep neural networks. In 51st Asilomar Conference on Signals, Systems, and Computers. IEEE, 1916\u20131920."},{"key":"e_1_3_1_81_2","first-page":"10201","volume-title":"IEEE\/CVF International Conference on Computer Vision (ICCV\u201921)","author":"Yao Man","year":"2021","unstructured":"Man Yao, Huanhuan Gao, Guangshe Zhao, Dingheng Wang, Yihan Lin, Zhaoxu Yang, and Guoqi Li. 2021. Temporal-wise attention spiking neural networks for event streams classification. In IEEE\/CVF International Conference on Computer Vision (ICCV\u201921). 10201\u201310210."},{"key":"e_1_3_1_82_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-020-1942-4"},{"key":"e_1_3_1_83_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-019-11786-6"},{"key":"e_1_3_1_84_2","first-page":"1068","volume-title":"Design, Automation & Test in Europe Conference & Exhibition (DATE\u201921)","author":"Zhang Grace Li","year":"2021","unstructured":"Grace Li Zhang, Bing Li, Xing Huang, Chen Shen, Shuhang Zhang, Florin Burcea, Helmut Graeb, Tsung-Yi Ho, Hai Li, and Ulf Schlichtmann. 2021. An efficient programming framework for memristor-based neuromorphic computing. In Design, Automation & Test in Europe Conference & Exhibition (DATE\u201921). IEEE, 1068\u20131073."},{"key":"e_1_3_1_85_2","doi-asserted-by":"publisher","DOI":"10.3390\/s20195558"},{"key":"e_1_3_1_86_2","doi-asserted-by":"crossref","unstructured":"Yunping Zhao Sheng Ma Hengzhu Liu Libo Huang and Yi Dai. 2023. SAC: An ultra-efficient spin-based architecture for compressed DNNs. ACM Transactions on Architecture and Code Optimization 21 1 (2023).","DOI":"10.1145\/3632957"},{"issue":"1","key":"e_1_3_1_87_2","doi-asserted-by":"crossref","first-page":"408","DOI":"10.1038\/s41467-020-20692-1","article-title":"Dynamic memristor-based reservoir computing for high-efficiency temporal signal processing","volume":"12","author":"Zhong Yanan","year":"2021","unstructured":"Yanan Zhong, Jianshi Tang, Xinyi Li, Bin Gao, He Qian, and Huaqiang Wu. 2021. Dynamic memristor-based reservoir computing for high-efficiency temporal signal processing. Nat. Commun. 12, 1 (2021), 408.","journal-title":"Nat. Commun."},{"key":"e_1_3_1_88_2","first-page":"2380","volume-title":"IEEE\/CVF International Conference on Computer Vision (ICCV\u201921)","author":"Zhu Lin","year":"2021","unstructured":"Lin Zhu, Jianing Li, Xiao Wang, Tiejun Huang, and Yonghong Tian. 2021. NeuSpike-Net: High speed video reconstruction via bio-inspired neuromorphic cameras. In IEEE\/CVF International Conference on Computer Vision (ICCV\u201921). 2380\u20132389."},{"key":"e_1_3_1_89_2","article-title":"Neural network distiller: A Python package for DNN compression research","author":"Zmora Neta","year":"2019","unstructured":"Neta Zmora, Guy Jacob, Lev Zlotnik, Bar Elharar, and Gal Novik. 2019. Neural network distiller: A Python package for DNN compression research. arXiv preprint arXiv:1910.12232 (2019).","journal-title":"arXiv preprint arXiv:1910.12232"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3643134","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3643134","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:21Z","timestamp":1750264281000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3643134"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3,14]]},"references-count":88,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2024,5,31]]}},"alternative-id":["10.1145\/3643134"],"URL":"https:\/\/doi.org\/10.1145\/3643134","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,3,14]]},"assertion":[{"value":"2023-05-23","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-01-21","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-03-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}