{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,29]],"date-time":"2025-11-29T08:02:07Z","timestamp":1764403327419,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"6","license":[{"start":{"date-parts":[[2024,9,11]],"date-time":"2024-09-11T00:00:00Z","timestamp":1726012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2024,11,30]]},"abstract":"<jats:p>\n            In-memory processing is becoming a popular method to alleviate the memory bottleneck of the Von Neumann computing model. With the goal of improving both latency and energy cost associated with such in-memory processing, emerging non-volatile memory technologies, such as Spintronic magnetic memory, are of particular interest, as they can provide a near-SRAM read\/write performance and eliminate nearly all static energy without experiencing any endurance limitations. Spintronic Racetrack Memory (RM) further addresses density concerns of spin-transfer torque memory (STT-MRAM). Moreover, it has recently been demonstrated that portions of RM nanowires can function as a polymorphic gate, which can be leveraged to implement multi-operand bulk bitwise operations. With more complex control, they can also be leveraged to build arithmetic integer and floating point processing in memory (PIM) primitives. This article proposes SPIMulator, a Spintronic PIM sim\n            <jats:italic>ulator<\/jats:italic>\n            that can simulate the storage and PIM architecture of executing PIM commands in Racetrack memory. SPIMulator functionally models the polymorphic gate properties recently proposed for Racetrack memory, which allows\n            <jats:italic>transverse access<\/jats:italic>\n            that determines the number of \u201c1\u201ds in a segment of each Racetrack nanowire. From this simulation, SPIMulator can report real-time performance statistics such as cycle count and energy. Thus, SPIMulator simulates the multi-operand bit-wise logic operations recently proposed and can be easily extended to implement new PIM operations as they are developed. Due to the functional nature of SPIMulator, it can serve as a programming environment that allows development of PIM-based codes for verification of new acceleration algorithms. We demonstrate the value of SPIMulator through the modeling and estimations of performance and energy consumption of a variety of example applications, including the Advanced Encryption Standard (AES) for encryption primarily based on logical and look-up operations; multiplication of matrices, a frequent requirement in scientific, signal processing, and machine learning algorithms; and bitmap indices, a common search table employed for database lookups.\n          <\/jats:p>","DOI":"10.1145\/3645112","type":"journal-article","created":{"date-parts":[[2024,2,8]],"date-time":"2024-02-08T12:05:12Z","timestamp":1707393912000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["SPIMulator: A Spintronic Processing-in-memory Simulator for Racetracks"],"prefix":"10.1145","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3495-617X","authenticated-orcid":false,"given":"Pavia","family":"Bera","sequence":"first","affiliation":[{"name":"University of South Florida, Tampa, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-1167-1187","authenticated-orcid":false,"given":"Stephen","family":"Cahoon","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3876-3578","authenticated-orcid":false,"given":"Sanjukta","family":"Bhanja","sequence":"additional","affiliation":[{"name":"University of South Florida, Tampa, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7498-0206","authenticated-orcid":false,"suffix":"Ph.D.","given":"Alex","family":"Jones","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,9,11]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131575"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2975719"},{"key":"e_1_3_2_4_2","volume-title":"the Non-volatile Memories Workshop","author":"Chen Y.-C.","year":"2012","unstructured":"Y.-C. Chen, H. Li, and W. Zhang. 2012. A RRAM-based memory system and applications. In the Non-volatile Memories Workshop."},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2023.3298920"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","unstructured":"Morris Dworkin Elaine Barker James Nechvatal James Foti Lawrence Bassham E. Roback and James Dray. 2001. Advanced Encryption Standard (AES). DOI:10.6028\/NIST.FIPS.197","DOI":"10.6028\/NIST.FIPS.197"},{"issue":"6","key":"e_1_3_2_7_2","first-page":"33","article-title":"Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects","volume":"18","author":"Huai Yiming","year":"2008","unstructured":"Yiming Huai. 2008. Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects. AAPPS Bull. 18, 6 (2008), 33\u201340.","journal-title":"AAPPS Bull."},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2019.2899306"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3257509"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3372489"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA\/IUCC.2017.00061"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/977091.977115"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00060"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3188206"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3195761"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2015.41"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1126\/science.1145799"},{"key":"e_1_3_2_19_2","first-page":"392","volume-title":"IEEE Computer Society Annual Symposium on VLSI","author":"Poremba M.","year":"2012","unstructured":"M. Poremba and Y. Xie. 2012. NVMain: An architectural-level main memory simulator for emerging non-volatile memories. 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Zhang, G. Sun, W. Zhang, F. Mi, H. Li, , and W. Zhao. 2015. Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. 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