{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T22:33:31Z","timestamp":1774478011978,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3655673","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4415-0866","authenticated-orcid":false,"given":"Anni","family":"Lu","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6092-6436","authenticated-orcid":false,"given":"Junmo","family":"Lee","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5793-075X","authenticated-orcid":false,"given":"Yuan-Chun","family":"Luo","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7668-569X","authenticated-orcid":false,"given":"Hai","family":"Li","sequence":"additional","affiliation":[{"name":"Exploratory Integrated Circuits, Components Research, Intel Corporation, Hillsboro, OR, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4017-5265","authenticated-orcid":false,"given":"Ian","family":"Young","sequence":"additional","affiliation":[{"name":"Exploratory Integrated Circuits, Components Research, Intel Corporation, Hillsboro, OR, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"32","article-title":"A (slightly) improved approximation algorithm for metric TSP","author":"Karlin A. R.","year":"2021","unstructured":"A. R. Karlin, et al., \"A (slightly) improved approximation algorithm for metric TSP,\" ACM SIGACT STOC, pp. 32--45, 2021.","journal-title":"ACM SIGACT STOC"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218695"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2023.3244485"},{"issue":"1","key":"e_1_3_2_1_4_1","first-page":"303","article-title":"A 20k-spin Ising chip to solve combinatorial optimization problems with CMOS annealing","volume":"51","author":"Yamaoka M.","year":"2015","unstructured":"M. Yamaoka, et al., \"A 20k-spin Ising chip to solve combinatorial optimization problems with CMOS annealing,\" IEEE JSSC, 51(1), pp. 303--309, 2015.","journal-title":"IEEE JSSC"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-58112-1_22"},{"key":"e_1_3_2_1_6_1","volume-title":"An 89TOPS\/W and 16.3 TOPS\/mm 2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications,\" IEEE ISSCC","author":"Chih Y.-D.","year":"2021","unstructured":"Y.-D. Chih, et al., \"An 89TOPS\/W and 16.3 TOPS\/mm 2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications,\" IEEE ISSCC, 2021."},{"key":"e_1_3_2_1_7_1","volume-title":"A 12nm 121-TOPS\/W 41.6-TOPS\/mm2 all digital full precision SRAM-based compute-in-memory with configurable bit-width for AI edge applications,\" IEEE VLSI","author":"Lee C.-F.","year":"2022","unstructured":"C.-F. Lee, et al., \"A 12nm 121-TOPS\/W 41.6-TOPS\/mm2 all digital full precision SRAM-based compute-in-memory with configurable bit-width for AI edge applications,\" IEEE VLSI, 2022."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731754"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3092533"},{"key":"e_1_3_2_1_10_1","first-page":"324","volume-title":"PMLR","author":"Gonzalez J.","year":"2011","unstructured":"J. Gonzalez, et al., \"Parallel Gibbs sampling: From colored fields to thin junction trees,\" AISTATS, PMLR, pp. 324--332, 2011."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1287\/ijoc.3.4.376"},{"key":"e_1_3_2_1_12_1","volume-title":"DNN+NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,\" IEEE IEDM","author":"Peng X.","year":"2019","unstructured":"X. Peng, et al., \"DNN+NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,\" IEEE IEDM, 2019."},{"key":"e_1_3_2_1_13_1","unstructured":"Concorde Benchmarks (from 1999) https:\/\/www.math.uwaterloo.ca\/tsp\/concorde\/benchmarks\/bench99.html."},{"key":"e_1_3_2_1_14_1","volume-title":"Massively simulating adiabatic bifurcations with FPGA to solve combinatorial optimization,\" ACM\/SIGDA FPGA","author":"Zou Y.","year":"2020","unstructured":"Y. Zou and M. Lin, \"Massively simulating adiabatic bifurcations with FPGA to solve combinatorial optimization,\" ACM\/SIGDA FPGA, 2020."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1126\/sciadv.abe7953"},{"key":"e_1_3_2_1_16_1","volume-title":"Efficient traveling salesman problem solvers using the Ising model with simulated bifurcation,\" DATE","author":"Zhang T.","year":"2022","unstructured":"T. Zhang and J. Han, \" Efficient traveling salesman problem solvers using the Ising model with simulated bifurcation,\" DATE, 2022."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2023.3243260"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"K. Yamamoto et al. \"STATICA: A 512-spin 0.25M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions \" IEEE ISSCC 2020.","DOI":"10.1109\/ISSCC19947.2020.9062965"},{"key":"e_1_3_2_1_19_1","volume-title":"Solving traveling salesman problems via a parallel fully connected Ising machine,\" ACM\/IEEE DAC","author":"Tao Q.","year":"2022","unstructured":"Q. Tao, and J. Han, \"Solving traveling salesman problems via a parallel fully connected Ising machine,\" ACM\/IEEE DAC, 2022."},{"key":"e_1_3_2_1_20_1","volume-title":"Accelerating Adaptive Parallel Tempering with FPGA-based p-bits,\" IEEE VLSI","author":"Aadit N.A.","year":"2023","unstructured":"N.A. Aadit, et al., \"Accelerating Adaptive Parallel Tempering with FPGA-based p-bits,\" IEEE VLSI, 2023."},{"key":"e_1_3_2_1_21_1","first-page":"1","article-title":"Neuro-Ising: Accelerating large scale travelling salesman problems via graph neural network guided localized Ising solvers","author":"Sanyal S.","year":"2022","unstructured":"S. Sanyal, K. Roy, \"Neuro-Ising: Accelerating large scale travelling salesman problems via graph neural network guided localized Ising solvers\", IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., pp. 1--1, 2022.","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"e_1_3_2_1_22_1","first-page":"480","volume-title":"CIM-spin: A 0.5-to-1.2 V scalable annealing processor using digital compute-in-memory spin operators and register-based spins for combinatorial optimization problems,\" IEEE ISSCC","author":"Su Y.","year":"2020","unstructured":"Y. Su, et al., \"CIM-spin: A 0.5-to-1.2 V scalable annealing processor using digital compute-in-memory spin operators and register-based spins for combinatorial optimization problems,\" IEEE ISSCC, pp. 480--482, 2020."},{"key":"e_1_3_2_1_23_1","volume-title":"A 144Kb annealing system composed of 9\u00d716Kb annealing processor chips with scalable chip-to-chip connections for large-scale combinatorial optimization problems,\" IEEE ISSCC","author":"Takemoto T.","year":"2021","unstructured":"T. Takemoto, et al., \"A 144Kb annealing system composed of 9\u00d716Kb annealing processor chips with scalable chip-to-chip connections for large-scale combinatorial optimization problems,\" IEEE ISSCC, 2021."},{"key":"e_1_3_2_1_24_1","volume-title":"Flexspin: A scalable CMOS Ising machine with 256 flexible spin processing elements for solving complex combinatorial optimization problems,\" IEEE ISSCC","author":"Su Y.","year":"2022","unstructured":"Y. Su, et al., \" Flexspin: A scalable CMOS Ising machine with 256 flexible spin processing elements for solving complex combinatorial optimization problems,\" IEEE ISSCC, 2022."},{"key":"e_1_3_2_1_25_1","volume-title":"Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension,\" IEEE ISSCC","author":"Kawamura K.","year":"2023","unstructured":"K. Kawamura, et al., \"Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension,\" IEEE ISSCC, 2023."}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA","acronym":"DAC '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655673","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3655673","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3655673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:48Z","timestamp":1750295868000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655673"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":25,"alternative-id":["10.1145\/3649329.3655673","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3655673","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}