{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T10:08:52Z","timestamp":1764842932539,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1942900"],"award-info":[{"award-number":["1942900"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3655930","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7539-8250","authenticated-orcid":false,"given":"Weidong","family":"Cao","sequence":"first","affiliation":[{"name":"The George Washington University, Washington, DC, United States"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-4757-5376","authenticated-orcid":false,"given":"Jian","family":"Gao","sequence":"additional","affiliation":[{"name":"Northeastern University, Boston, MA, United States"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0952-2115","authenticated-orcid":false,"given":"Xin","family":"Xin","sequence":"additional","affiliation":[{"name":"University of Central Florida, Orlando, FL, United States"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0482-5435","authenticated-orcid":false,"given":"Xuan","family":"Zhang","sequence":"additional","affiliation":[{"name":"Northeastern University, Boston, MA, United States"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_3_2_1_1_1","DOI":"10.1109\/ISCAS46773.2023.10181895"},{"key":"e_1_3_2_1_2_1","first-page":"2142","article-title":"Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals","volume":"71","author":"Cao Weidong","year":"2022","unstructured":"Weidong Cao, Yilong Zhao, and et al. 2022. Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals. IEEE Trans. Comput. 71, 9 (2022), 2142--2155.","journal-title":"IEEE Trans. Comput."},{"key":"e_1_3_2_1_3_1","volume-title":"2021 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"64","author":"Chih Yu-Der","unstructured":"Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, and et al. 2021. 16.4 An 89TOPS\/W and 16.3TOPS\/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. In 2021 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 64. 252--254."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1145\/3361682"},{"key":"e_1_3_2_1_5_1","volume-title":"2022 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"65","author":"Fujiwara Hidehiro","unstructured":"Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, and et al. 2022. A 5-nm 254-TOPS\/W 221-TOPS\/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. In 2022 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 65. 1--3."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1145\/3307650.3322237"},{"volume-title":"2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 1--14","author":"Jouppi Norman P.","unstructured":"Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, and et al. 2021. Ten Lessons From Three Generations Shaped Google's TPUv4i: Industrial Product. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 1--14.","key":"e_1_3_2_1_7_1"},{"key":"e_1_3_2_1_8_1","volume-title":"GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. In 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA). 249--262","author":"Kim Heesu","year":"2021","unstructured":"Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, and Jinho Lee. 2021. GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent. In 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA). 249--262."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1109\/TC.2020.3000218"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1145\/3531437.3539706"},{"unstructured":"Peter Mattson Christine Cheng and et al. 2020. MLPerf Training Benchmark. arXiv:cs.LG\/1910.01500","key":"e_1_3_2_1_11_1"},{"unstructured":"Paulius Micikevicius Dusan Stosic and et al. 2022. FP8 Formats for Deep Learning. arXiv:cs.LG\/2209.05433","key":"e_1_3_2_1_12_1"},{"unstructured":"Vijay Janapa Reddi Christine Cheng and et al. 2020. MLPerf Inference Benchmark. arXiv:cs.LG\/1911.02549","key":"e_1_3_2_1_13_1"},{"volume-title":"2021 IEEE International Solid-State Circuits Conference (ISSCC). 250--252","author":"Su Jian-Wei","unstructured":"Jian-Wei Su, Yen-Chi Chou, and et al. 2021. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. In 2021 IEEE International Solid-State Circuits Conference (ISSCC). 250--252.","key":"e_1_3_2_1_14_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1109\/TCAD.2023.3333290"},{"unstructured":"Fengbin Tu and et al. 2022. A 28nm 29.2TFLOPS\/W BF16 and 36.5TOPS\/W INT8 Reconfigurable Digital CIM Processor with Unified FP\/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. In 2022 IEEE International Solid-State Circuits Conference (ISSCC). 1--3.","key":"e_1_3_2_1_16_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"e_1_3_2_1_18_1","volume-title":"2022 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"65","author":"Wu Ping-Chun","unstructured":"Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, and et al. 2022. A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS\/W for 8b-MAC Operations for Edge-AI Devices. In 2022 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 65. 1--3."},{"volume-title":"2023 IEEE International Solid-State Circuits Conference (ISSCC). 126--128","author":"Wu Ping-Chun","unstructured":"Ping-Chun Wu, Jian-Wei Su, and et al. 2023. A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS\/W for High-Accuracy AI-Edge Devices. In 2023 IEEE International Solid-State Circuits Conference (ISSCC). 126--128.","key":"e_1_3_2_1_19_1"},{"key":"e_1_3_2_1_20_1","volume-title":"Quantization Networks. In Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR).","author":"Yang Jiwei","year":"2019","unstructured":"Jiwei Yang, Xu Shen, Jun Xing, Xinmei Tian, Houqiang Li, Bing Deng, Jianqiang Huang, and Xian-sheng Hua. 2019. Quantization Networks. In Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR)."},{"volume-title":"2023 IEEE International Solid-State Circuits Conference (ISSCC). 1--3.","author":"Yue Jinshan","unstructured":"Jinshan Yue, Chaojie He, and et al. 2023. A 28nm 16.9-300TOPS\/W Computing-in-Memory Processor Supporting Floating-Point NN Inference\/Training with Intensive-CIM Sparse-Digital Architecture. In 2023 IEEE International Solid-State Circuits Conference (ISSCC). 1--3.","key":"e_1_3_2_1_21_1"},{"key":"e_1_3_2_1_22_1","volume-title":"Jingli Wang, Ning Zhang, Ziyuan Lin, Shimeng Yu, Jinfeng Kang, H-S Philip Wong, et al.","author":"Zhou Feichi","year":"2019","unstructured":"Feichi Zhou, Zheng Zhou, Jiewei Chen, Tsz Hin Choy, Jingli Wang, Ning Zhang, Ziyuan Lin, Shimeng Yu, Jinfeng Kang, H-S Philip Wong, et al. 2019. Optoelectronic resistive random access memory for neuromorphic vision sensors. Nature nanotechnology 14, 8 (2019), 776--782."}],"event":{"sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"acronym":"DAC '24","name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA"},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655930","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3655930","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3655930","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:48Z","timestamp":1750295868000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655930"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":22,"alternative-id":["10.1145\/3649329.3655930","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3655930","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}