{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:52:22Z","timestamp":1780674742921,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3655965","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["4-Transistor Ternary Content Addressable Memory Cell Design using Stacked Hybrid IGZO\/Si Transistors"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0177-8933","authenticated-orcid":false,"given":"Munhyeon","family":"Kim","sequence":"first","affiliation":[{"name":"Seoul National University, Seoul, Seoul, Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5175-8258","authenticated-orcid":false,"given":"Jae-Joon","family":"Kim","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul, Seoul, Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"IEEE","author":"Stas S.","year":"1993","unstructured":"S. Stas, \"Associative processing with cams,\" in Proceedings of NORTHCON'93 Electrical and Electronics Convention, pp. 161--167, IEEE, 1993."},{"key":"e_1_3_2_1_2_1","volume-title":"Content-addressable memory (cam) circuits and architectures: A tutorial and survey,\" IEEE journal of solid-state circuits","author":"Pagiamtzis K.","unstructured":"K. Pagiamtzis and A. Sheikholeslami, \"Content-addressable memory (cam) circuits and architectures: A tutorial and survey,\" IEEE journal of solid-state circuits, vol. 41, no. 3, pp. 712--727, 2006."},{"key":"e_1_3_2_1_3_1","first-page":"2350","volume-title":"GLOBECOM'02","volume":"3","author":"Qin G.","year":"2002","unstructured":"G. Qin, S. Ata, I. Oka, and C. Fujiwara, \"Effective bit selection methods for improving performance of packet classifications on ip routers,\" in Global Telecommunications Conference, 2002. GLOBECOM'02. IEEE, vol. 3, pp. 2350--2354, IEEE, 2002."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.802001"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0321-3"},{"key":"e_1_3_2_1_6_1","first-page":"240","volume-title":"13.6 a 28nm 400mhz 4-parallel 1.6 gsearch\/s 80mb ternary cam,\" in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)","author":"Nii K.","year":"2014","unstructured":"K. Nii, T. Amano, N. Watanabe, M. Yamawaki, K. Yoshinaga, M. Wada, and I. Hayashi, \"13.6 a 28nm 400mhz 4-parallel 1.6 gsearch\/s 80mb ternary cam,\" in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 240--241, IEEE, 2014."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001932"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274888"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2019.2942456"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3107497"},{"issue":"6","key":"e_1_3_2_1_11_1","first-page":"700","article-title":"A 10t-4mtj nonvolatile ternary cam cell for reliable search operation and a compact area","volume":"64","author":"Song B.","year":"2016","unstructured":"B. Song, T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung, \"A 10t-4mtj nonvolatile ternary cam cell for reliable search operation and a compact area,\" IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 6, pp. 700--704, 2016.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2023.3243222"},{"key":"e_1_3_2_1_13_1","volume-title":"1mb 0.41 \u03bcm 2 2t-2r cell nonvolatile tcam with two-bit encoding and clocked self-referenced sensing,\" in 2013 Symposium on VLSI Technology","author":"Li J.","year":"2013","unstructured":"J. Li, R. Montoye, M. Ishii, K. Stawiasz, T. Nishida, K. Maloney, G. Ditlow, S. Lewis, T. Maffitt, R. Jordan, et al., \"1mb 0.41 \u03bcm 2 2t-2r cell nonvolatile tcam with two-bit encoding and clocked self-referenced sensing,\" in 2013 Symposium on VLSI Technology, pp. C104--C105, IEEE, 2013."},{"key":"e_1_3_2_1_14_1","unstructured":"L. Wang W. Ye J. Lai J. Liu J. Yang X. Si C. Huo C. Dou X. Xu Q. Liu et al. \"A 14nm 100kb 2t1r transpose rram with> 150x resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme \" in 2021 Symposium on VLSI Technology pp. 1--2 IEEE 2021."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830374"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2010.2099201"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"A. Belmonte H. Oh S. Subhechha N. Rassoul H. Hody H. Dekkers R. Delhougne L. Ricotti K. Banerjee A. Chasin et al. \"Tailoring igzo-tft architecture for capacitorless dram demonstrating> 10 3 s retention > 10 11 cycles endurance and l g scalability down to 14nm \" in 2021 IEEE International Electron Devices Meeting (IEDM) pp. 10--6 IEEE 2021.","DOI":"10.1109\/IEDM19574.2021.9720596"},{"key":"e_1_3_2_1_18_1","first-page":"3","volume-title":"3d-stacked caac-in-ga-zn oxide fets with gate length of 72nm,\" in 2019 IEEE International Electron Devices Meeting (IEDM)","author":"Oota M.","year":"2019","unstructured":"M. Oota, Y. Ando, K. Tsuda, T. Koshida, S. Oshita, A. Suzuki, K. Fukushima, S. Nagatsuka, T. Onuki, R. Hodo, et al., \"3d-stacked caac-in-ga-zn oxide fets with gate length of 72nm,\" in 2019 IEEE International Electron Devices Meeting (IEDM), pp. 3--2, IEEE, 2019."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"K. Huang X. Duan J. Feng Y. Sun C. Lu C. Chen G. Jiao X. Lin J. Shao S. Yin J. Sheng Z. Wang W. Zhang X. Chuai J. Niu W. Wang Y. Wu W. Jing Z. Wang J. Xu G. Yang D. Geng L. Li and M. Liu \"Vertical channel-all-around (caa) igzo fet under 50 nm cd with high read current of 32.8 \u03bca\/\u03bcm (vth + 1 v) well-performed thermal stability up to 120 \u00b0C for low latency high-density 2t0c 3d dram application \" in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 296--297 2022.","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830271"},{"key":"e_1_3_2_1_20_1","first-page":"3","volume-title":"3d-stacked caac-in-ga-zn oxide fets with gate length of 72nm,\" in 2019 IEEE International Electron Devices Meeting (IEDM)","author":"Oota M.","year":"2019","unstructured":"M. Oota, Y. Ando, K. Tsuda, T. Koshida, S. Oshita, A. Suzuki, K. Fukushima, S. Nagatsuka, T. Onuki, R. Hodo, et al., \"3d-stacked caac-in-ga-zn oxide fets with gate length of 72nm,\" in 2019 IEEE International Electron Devices Meeting (IEDM), pp. 3--2, IEEE, 2019."},{"key":"e_1_3_2_1_21_1","first-page":"59","volume-title":"True 7nm platform technology featuring smallest finfet and smallest sram cell by euv, special constructs and 3 rd generation single diffusion break,\" in 2018 IEEE Symposium on VLSI Technology","author":"Jeong W.","year":"2018","unstructured":"W. Jeong, S. Maeda, H. Lee, K. Lee, T. Lee, D. Park, B. Kim, J. Do, T. Fukai, D. Kwon, et al., \"True 7nm platform technology featuring smallest finfet and smallest sram cell by euv, special constructs and 3 rd generation single diffusion break,\" in 2018 IEEE Symposium on VLSI Technology, pp. 59--60, IEEE, 2018."},{"key":"e_1_3_2_1_22_1","first-page":"1","volume-title":"Improved air spacer co-integrated with self-aligned contact (sac) and contact over active gate (coag) for highly scaled cmos technology,\" in 2020 IEEE Symposium on VLSI Technology","author":"Cheng K.","year":"2020","unstructured":"K. Cheng, C. Park, H. Wu, J. Li, S. Nguyen, J. Zhang, M. Wang, S. Mehta, Z. Liu, R. Conti, et al., \"Improved air spacer co-integrated with self-aligned contact (sac) and contact over active gate (coag) for highly scaled cmos technology,\" in 2020 IEEE Symposium on VLSI Technology, pp. 1--2, IEEE, 2020."},{"key":"e_1_3_2_1_23_1","unstructured":"S.-Y. Wu C. Lin M. Chiang J. Liaw J. Cheng S. Yang C. Tsai P. Chen T. Miyashita C. Chang V. Chang K. Pan J. Chen Y. Mor K. Lai C. Liang H. Chen S. Chang C. Lin C. Hsieh R. Tsui C. Yao C. Chen R. Chen C. Lee H. Lin C. Chang K. Chen M. Tsai K. Chen Y. Ku and S. M. Jang \"A 7nm cmos platform technology featuring 4th generation finfet transistors with a 0.027um2 high density 6-t sram cell for mobile soc applications \" in 2016 IEEE International Electron Devices Meeting (IEDM) pp. 2.6.1--2.6.4 2016."},{"key":"e_1_3_2_1_24_1","volume-title":"Stacked nanosheet gate-all-around transistor to enable scaling beyond finfet,\" in 2017 Symposium on VLSI Technology","author":"Loubet N.","year":"2017","unstructured":"N. Loubet, T. Hook, P. Montanini, C.-W. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, X. Miao, J. Wang, et al., \"Stacked nanosheet gate-all-around transistor to enable scaling beyond finfet,\" in 2017 Symposium on VLSI Technology, pp. T230--T231, IEEE, 2017."}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA","acronym":"DAC '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655965","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3655965","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:55Z","timestamp":1750295875000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655965"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":24,"alternative-id":["10.1145\/3649329.3655965","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3655965","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}