{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,22]],"date-time":"2025-12-22T18:34:44Z","timestamp":1766428484323,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"The National Natural Science Foundation of China (NSFC)","award":["62002340","61872336","and No.62090020"],"award-info":[{"award-number":["62002340","61872336","and No.62090020"]}]},{"name":"The Strategic Priority Research Program of the CAS","award":["XDB44030100"],"award-info":[{"award-number":["XDB44030100"]}]},{"name":"The Youth Innovation Promotion Association CAS","award":["Y201923"],"award-info":[{"award-number":["Y201923"]}]},{"name":"The Internship Program of YUSUR Technology Co., Ltd."}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3655967","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9516-2648","authenticated-orcid":false,"given":"Yunkun","family":"Liao","sequence":"first","affiliation":[{"name":"State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"},{"name":"University of Chinese Academy of Sciences, Beijing, Beijing, China"},{"name":"Zhongguancun Laboratory, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4938-5899","authenticated-orcid":false,"given":"Jingya","family":"Wu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-1881-962X","authenticated-orcid":false,"given":"Wenyan","family":"Lu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"},{"name":"YUSUR Technology Co., Ltd, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0874-814X","authenticated-orcid":false,"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"},{"name":"Zhongguancun Laboratory, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1254-3278","authenticated-orcid":false,"given":"Guihai","family":"Yan","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"},{"name":"YUSUR Technology Co., Ltd, Beijing, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Profiling a warehouse-scale computer.\" In ACM\/IEEE ISCA","author":"Kanev Svilen","year":"2015","unstructured":"Kanev, Svilen, et al. \"Profiling a warehouse-scale computer.\" In ACM\/IEEE ISCA 2015."},{"key":"e_1_3_2_1_2_1","volume-title":"Parallel Huffman decoder with an optimized look up table option on FPGA.\" In IEEE TENCON","author":"Aspar","year":"2000","unstructured":"Z. Aspar, et al, \"Parallel Huffman decoder with an optimized look up table option on FPGA.\" In IEEE TENCON, 2000."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2022.09.015"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1984.1056931"},{"key":"e_1_3_2_1_5_1","volume-title":"Massively parallel Huffman decoding on GPUs.\" In ACM ICPP","author":"Wei\u00dfenberger Andr\u00e9","year":"2018","unstructured":"Wei\u00dfenberger, Andr\u00e9, et al. \"Massively parallel Huffman decoding on GPUs.\" In ACM ICPP, 2018."},{"key":"e_1_3_2_1_6_1","volume-title":"Huffman coding with gap arrays for GPU acceleration.\" In ACM ICPP","author":"Yamamoto Naoya","year":"2020","unstructured":"Yamamoto, Naoya, et al. \"Huffman coding with gap arrays for GPU acceleration.\" In ACM ICPP, 2020."},{"key":"e_1_3_2_1_7_1","volume-title":"Optimizing huffman decoding for error-bounded lossy compression on gpus.\" In IEEE IPDPS","author":"Rivera Cody","year":"2022","unstructured":"Rivera, Cody, et al. \"Optimizing huffman decoding for error-bounded lossy compression on gpus.\" In IEEE IPDPS, 2022."},{"key":"e_1_3_2_1_8_1","volume-title":"A network-centric hardware\/algorithm co-design to accelerate distributed training of deep neural networks.\" In IEEE MICRO","author":"Li Youjie","year":"2018","unstructured":"Li, Youjie, et al. \"A network-centric hardware\/algorithm co-design to accelerate distributed training of deep neural networks.\" In IEEE MICRO, 2018."},{"key":"e_1_3_2_1_9_1","volume-title":"A High-performance FPGA-based Accelerator for Gradient Compression.\" In IEEE DCC","author":"Ren Qingqing","year":"2022","unstructured":"Ren, Qingqing, et al. \"A High-performance FPGA-based Accelerator for Gradient Compression.\" In IEEE DCC, 2022."},{"key":"e_1_3_2_1_10_1","unstructured":"AMD Xilinx. \"Vitis Accelerated Libraries.\" https:\/\/www.xilinx.com\/products\/design-tools\/vitis\/vitis-libraries.html."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.17487\/RFC7541"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/46.5.487"},{"key":"e_1_3_2_1_13_1","volume-title":"Programmable packet scheduling at line rate.\" Proceedings of the 2016 ACM SIGCOMM Conference","author":"Sivaraman Anirudh","year":"2016","unstructured":"Sivaraman, Anirudh, et al. \"Programmable packet scheduling at line rate.\" Proceedings of the 2016 ACM SIGCOMM Conference. 2016."}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco CA USA","acronym":"DAC '24"},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655967","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3655967","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:55Z","timestamp":1750295875000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3655967"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":13,"alternative-id":["10.1145\/3649329.3655967","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3655967","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}