{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T02:00:27Z","timestamp":1782352827289,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3656243","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1322-5642","authenticated-orcid":false,"given":"Yuan","family":"Pu","sequence":"first","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, Hong Kong, Hong Kong Special Administrative Region of China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-9370-4504","authenticated-orcid":false,"given":"Fangzhou","family":"Liu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, Hong Kong, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-7835-3024","authenticated-orcid":false,"given":"Yu","family":"Zhang","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, Hong Kong, Hong Kong Special Administrative Region of China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-4909-6588","authenticated-orcid":false,"given":"Zhuolun","family":"He","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, Hong Kong, Hong Kong Special Administrative Region of China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-2774","authenticated-orcid":false,"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-1057-1319","authenticated-orcid":false,"given":"Kai-Yuan","family":"Chao","sequence":"additional","affiliation":[{"name":"Siemens Digital Industries Software, Wilsonville, Oregon, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6406-4810","authenticated-orcid":false,"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Shatin, N\/A, Hong Kong Special Administrative Region of China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"M. Hatamian and P. Penzes \"Non-integer height standard cell library \" Patent uS Patent 8 788 998."},{"key":"e_1_3_2_1_2_1","volume-title":"IEDM","author":"Wu S.-Y.","year":"2022","unstructured":"S.-Y. Wu, C. Chang, M. Chiang, C. Lin, J. Liaw, J. Cheng, J. Yeh, H. Chen, S. Chang, K. Lai et al., \"A 3nm CMOS FinFlex\u2122 Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications,\" in Proc. IEDM, 2022."},{"issue":"4","key":"e_1_3_2_1_3_1","first-page":"855","article-title":"Design implementation with noninteger multiple-height cells for improved design quality in advanced nodes","volume":"37","author":"Dobre S. A.","year":"2017","unstructured":"S. A. Dobre, A. B. Kahng, and J. Li, \"Design implementation with noninteger multiple-height cells for improved design quality in advanced nodes,\" IEEE TCAD, vol. 37, no. 4, pp. 855--868, 2017.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_4_1","volume-title":"ICCAD","author":"Lin Z.-Y.","year":"2021","unstructured":"Z.-Y. Lin and Y.-W. Chang, \"A row-based algorithm for non-integer multiple-cell-height placement,\" in Proc. ICCAD, 2021."},{"key":"e_1_3_2_1_5_1","volume-title":"DAC","author":"Chen J.","year":"2020","unstructured":"J. Chen, Z. Huang, Y. Huang, W. Zhu, J. Yu, and Y.-W. Chang, \"An efficient epist algorithm for global placement with non-integer multiple-height cells,\" in Proc. DAC, 2020."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514940"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431578"},{"key":"e_1_3_2_1_8_1","volume-title":"ICCAD","author":"Ozdal M. M.","year":"2011","unstructured":"M. M. Ozdal, S. Burns, and J. Hu, \"Gate sizing and device technology selection algorithms for high-performance industrial designs,\" in Proc. ICCAD, 2011."},{"key":"e_1_3_2_1_9_1","volume-title":"Marakkalage et al., \"The epfl logic synthesis libraries,\" arXiv preprint arXiv:1805.05121","author":"Soeken M.","year":"2018","unstructured":"M. Soeken, H. Riener, W. Haaswijk, E. Testa, B. Schmitt, G. Meuli, F. Mozafari, S.-Y. Lee, A. T. Calvino, D. S. Marakkalage et al., \"The epfl logic synthesis libraries,\" arXiv preprint arXiv:1805.05121, 2018."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372666"},{"key":"e_1_3_2_1_11_1","volume-title":"ISPD","author":"Martins M.","year":"2015","unstructured":"M. Martins, J. M. Matos, R. P. Ribas, A. Reis, G. Schlinker, L. Rech, and J. Michelsen, \"Open cell library in 15nm freepdk technology,\" in Proc. ISPD, 2015."},{"key":"e_1_3_2_1_12_1","volume-title":"IWLS","author":"Amar\u00fa L.","year":"2015","unstructured":"L. Amar\u00fa, P.-E. Gaillardon, and G. De Micheli, \"The EPFL combinational benchmark suite,\" in Proc. IWLS, 2015."},{"issue":"1","key":"e_1_3_2_1_13_1","first-page":"70","article-title":"FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design","volume":"27","author":"Chu C.","year":"2007","unstructured":"C. Chu and Y.-C. Wong, \"FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design,\" IEEE TCAD, vol. 27, no. 1, pp. 70--83, 2007.","journal-title":"IEEE TCAD"}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA","acronym":"DAC '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3656243","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3656243","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:55Z","timestamp":1750295875000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3656243"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":13,"alternative-id":["10.1145\/3649329.3656243","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3656243","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}