{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:05:08Z","timestamp":1750309508254,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3656535","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["TraiNDSim: A Simulation Framework for Comprehensive Performance Evaluation of Neuromorphic Devices for On-Chip Training"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-0291-8164","authenticated-orcid":false,"given":"Donghyeok","family":"Heo","sequence":"first","affiliation":[{"name":"Sungkyunkwan University, Suwon, Gyeonggi-do, Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3153-3825","authenticated-orcid":false,"given":"Hyeonsu","family":"Bang","sequence":"additional","affiliation":[{"name":"Sungkyunkwan University, Suwon, Gyeonggi-do, Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4434-4318","authenticated-orcid":false,"given":"Jong Hwan","family":"Ko","sequence":"additional","affiliation":[{"name":"Sungkyunkwan University (SKKU), Suwon, Gyunggi, Republic of Korea"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"S. Agarwal et al. 2016. Resistive memory device requirements for a neural algorithm accelerator. In IEEE IJCNN. 929--938.","DOI":"10.1109\/IJCNN.2016.7727298"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2898443"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"P. Y. Chen et al. 2015. Mitigating effects of non-ideal synaptic device characteristics for on-chip learning. In IEEE\/ACM ICCAD. 194--199.","DOI":"10.1109\/ICCAD.2015.7372570"},{"key":"e_1_3_2_1_4_1","first-page":"12","article-title":"2018. NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning","volume":"37","author":"Chen P. Y.","year":"2018","unstructured":"P. Y. Chen et al. 2018. NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning. IEEE TCAD 37, 12 (2018), 3067--3080.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_5_1","volume-title":"DeGroot et al","author":"M.","year":"2012","unstructured":"M. H. DeGroot et al. 2012. Probability and statistics. Pearson Education."},{"key":"e_1_3_2_1_6_1","first-page":"3","article-title":"2020. XB-SIM: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design","volume":"26","author":"Fei X.","year":"2020","unstructured":"X. Fei et al. 2020. XB-SIM: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design. Tsinghua Science and Technology 26, 3 (2020), 322--334.","journal-title":"Tsinghua Science and Technology"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"K. He et al. 2015. Delving deep into rectifiers: Surpassing human-level performance on imagenet classification. In IEEE ICCV. 1026--1034.","DOI":"10.1109\/ICCV.2015.123"},{"key":"e_1_3_2_1_8_1","first-page":"9","article-title":"2018. Memristor-based analog computation and neural network classification with a dot product engine","volume":"30","author":"Hu M.","year":"2018","unstructured":"M. Hu et al. 2018. Memristor-based analog computation and neural network classification with a dot product engine. Advanced Materials 30, 9 (2018), 1705914.","journal-title":"Advanced Materials"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"M. Jerry et al. 2017. Ferroelectric FET analog synapse for acceleration of deep neural network training. In IEEE IEDM. 6--2.","DOI":"10.1109\/IEDM.2017.8268338"},{"key":"e_1_3_2_1_10_1","first-page":"3","article-title":"2018. Emerging memory technologies for neuromorphic computing","volume":"30","author":"Kim C. H.","year":"2018","unstructured":"C. H. Kim et al. 2018. Emerging memory technologies for neuromorphic computing. Nanotechnology 30, 3 (2018), 032001.","journal-title":"Nanotechnology"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776551"},{"key":"e_1_3_2_1_12_1","unstructured":"A. Krizhevsky et al. 2009. Learning multiple layers of features from tiny images. (2009)."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2022.02.043"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Y. LeCun et al. 1989. Backpropagation applied to handwritten zip code recognition. Neural computation 1 4 (1989) 541--551.","DOI":"10.1162\/neco.1989.1.4.541"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"C. Li et al. 2018. Analogue signal and image processing with large memristor crossbars. Nature electronics 1 1 (2018) 52--59.","DOI":"10.1038\/s41928-017-0002-z"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2963323"},{"key":"e_1_3_2_1_17_1","first-page":"11","article-title":"2020. DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training","volume":"40","author":"Peng X.","year":"2020","unstructured":"X. Peng et al. 2020. DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training. IEEE TCAD 40, 11 (2020), 2306--2319.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3219066"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"D. Querlioz et al. 2011. Learning with memristive devices: How should we model their behavior?. In IEEE\/ACM NANOARCH. 150--156.","DOI":"10.1109\/NANOARCH.2011.5941497"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-023-05759-5"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"M. J. Rasch et al. 2021. A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays. In IEEE AICAS. 1--4.","DOI":"10.1109\/AICAS51828.2021.9458494"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3063543"},{"key":"e_1_3_2_1_23_1","unstructured":"D. E. Rumelhart et al. 1985. Learning internal representations by error propagation. Technical Report. California Univ San Diego La Jolla Inst for Cognitive Science."},{"key":"e_1_3_2_1_24_1","unstructured":"K. Simonyan et al. 2014. Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556 (2014)."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"J. Tang et al. 2018. ECRAM as scalable synaptic cell for high-speed low-power neuromorphic computing. In IEEE IEDM. 13--1.","DOI":"10.1109\/IEDM.2018.8614551"},{"key":"e_1_3_2_1_26_1","unstructured":"S. Wu et al. 2018. Training and inference with integers in deep neural networks. arXiv preprint arXiv:1802.04680 (2018)."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510690"},{"key":"e_1_3_2_1_28_1","unstructured":"L. Yann et al. 2010. MNIST handwritten digit database. http:\/\/yann.lecun.com\/exdb\/mnist\/"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","unstructured":"Z. Zhu et al. 2020. MNSIM 2.0: A behavior-level modeling tool for memristor-based neuromorphic computing systems. In GLSVLSI. 83--88.","DOI":"10.1145\/3386263.3407647"}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"San Francisco CA USA","acronym":"DAC '24"},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3656535","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3656535","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:55Z","timestamp":1750295875000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3656535"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":29,"alternative-id":["10.1145\/3649329.3656535","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3656535","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}