{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T09:51:52Z","timestamp":1773827512320,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3657351","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Advanced gate-level glitch modeling using ANNs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3024-3455","authenticated-orcid":false,"given":"Anastasis","family":"Vagenas","sequence":"first","affiliation":[{"name":"University of Thessaly, Volos, Thessaly, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8616-2366","authenticated-orcid":false,"given":"Dimitrios","family":"Garyfallou","sequence":"additional","affiliation":[{"name":"University of Thessaly, Volos, Thessaly, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6968-0222","authenticated-orcid":false,"given":"Nestor","family":"Evmorfopoulos","sequence":"additional","affiliation":[{"name":"University of Thessaly, Volos, Thessaly, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2032-5094","authenticated-orcid":false,"given":"George","family":"Stamoulis","sequence":"additional","affiliation":[{"name":"University of Thessaly, Volos, Thessaly, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Nov. 17","year":"2023","unstructured":"Synopsys - What is Glitch Power? Accessed: Nov. 17, 2023. [Online]. Available: https:\/\/www.synopsys.com\/ai\/what-is-glitch-power.html"},{"key":"e_1_3_2_1_2_1","first-page":"123","volume-title":"Analysis of glitch power dissipation in CMOS ICs,\" in Proc. of the International Symposium on Low Power Design (ISLPD)","author":"Favalli M.","year":"1995","unstructured":"M. Favalli and L. Benini, \"Analysis of glitch power dissipation in CMOS ICs,\" in Proc. of the International Symposium on Low Power Design (ISLPD), pp. 123--128, 1995."},{"key":"e_1_3_2_1_3_1","first-page":"66","volume-title":"New approach in gate-level glitch modelling,\" in Proc. of the conference on European design automation (EURO-DAC)","author":"Rabe D.","year":"1996","unstructured":"D. Rabe and W. Nebel, \"New approach in gate-level glitch modelling,\" in Proc. of the conference on European design automation (EURO-DAC), pp. 66--71, 1996."},{"key":"e_1_3_2_1_4_1","unstructured":"J. A. Thodiyil \"Generic gate level model for characterization of glitch power in logic cells \" Nov. 25 1997 US Patent 5 691 910."},{"key":"e_1_3_2_1_5_1","first-page":"7","article-title":"Accurate estimation of CMOS power consumption considering glitches by using waveform lookup","volume":"64","author":"Meixner M.","year":"2017","unstructured":"M. Meixner and T. G. Noll, \"Accurate estimation of CMOS power consumption considering glitches by using waveform lookup,\" IEEE Trans. Circuits Syst. II Express Briefs, vol. 64-II, no. 7, pp. 787--791, 2017.","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"issue":"4","key":"e_1_3_2_1_6_1","first-page":"485","article-title":"Efficient delay characterization method to obtain the output waveform of logic gates considering glitches","volume":"15","author":"Abolmaali S.","year":"2019","unstructured":"S. Abolmaali, \"Efficient delay characterization method to obtain the output waveform of logic gates considering glitches,\" Iranian Journal of Electrical and Electronic Engineering, vol. 15, no. 4, p. 485, 2019.","journal-title":"Iranian Journal of Electrical and Electronic Engineering"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1611282"},{"key":"e_1_3_2_1_8_1","first-page":"467","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE)","author":"Clavijo P.","year":"2001","unstructured":"P. Ruiz-de-Clavijo, J. Juan-Chico, M. J. Bellido, A. J. Acosta, and M. Valencia-Barrero, \"HALOTIS: high accuracy logic timing simulator with inertial and degradation delay model,\" in Proc. of the Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 467--471, 2001."},{"key":"e_1_3_2_1_10_1","volume-title":"Nov. 17","year":"2023","unstructured":"Synopsys - Composite Current Source (CCS). Accessed: Nov. 17, 2023. [Online]. Available: http:\/\/www.opensourceliberty.org\/ccspaper\/"},{"key":"e_1_3_2_1_11_1","volume-title":"Nov. 17","year":"2023","unstructured":"Synopsys - PrimePower. Accessed: Nov. 17, 2023. [Online]. Available: https:\/\/www.synopsys.com\/implementation-and-signoff\/signoff\/primepower.html"},{"key":"e_1_3_2_1_12_1","first-page":"125","volume-title":"Short circuit power consumption of glitches,\" in Proc. of the International Symposium on Low Power Design (ISLPD)","author":"Rabe D.","year":"1996","unstructured":"D. Rabe and W. Nebel, \"Short circuit power consumption of glitches,\" in Proc. of the International Symposium on Low Power Design (ISLPD), pp. 125--128, 1996."},{"key":"e_1_3_2_1_13_1","first-page":"247","volume-title":"A multi-port current source model for multiple-input switching effects in CMOS library cells,\" in Proc. of the 43rd Design Automation Conference (DAC)","author":"Amin C. S.","year":"2006","unstructured":"C. S. Amin, C. V. Kashyap, N. Menezes, K. Killpack, and E. Chiprout, \"A multi-port current source model for multiple-input switching effects in CMOS library cells,\" in Proc. of the 43rd Design Automation Conference (DAC), pp. 247--252, 2006."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2876917"},{"key":"e_1_3_2_1_15_1","first-page":"514","volume-title":"Analytical model for the impact of multiple input switching noise on timing,\" in Proc. of the 13th Asia South Pacific Design Automation Conference (ASP-DAC)","author":"Tayade R.","year":"2008","unstructured":"R. Tayade, S. R. Nassif, and J. A. Abraham, \"Analytical model for the impact of multiple input switching noise on timing,\" in Proc. of the 13th Asia South Pacific Design Automation Conference (ASP-DAC), pp. 514--517, 2008."},{"key":"e_1_3_2_1_16_1","first-page":"1","volume-title":"Accurate soft error rate evaluation using event-driven dynamic timing analysis,\" in Proc. of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","author":"Paliaroutis G.-I.","year":"2023","unstructured":"G.-I. Paliaroutis et al., \"Accurate soft error rate evaluation using event-driven dynamic timing analysis,\" in Proc. of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1--6, 2023."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3061484"},{"key":"e_1_3_2_1_18_1","first-page":"225","volume-title":"Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation,\" in Proc. of the 21st International Symposium on Quality Electronic Design (ISQED)","author":"Garyfallou D.","year":"2020","unstructured":"D. Garyfallou, I. Tsiokanos, N. Evmorfopoulos, G. Stamoulis, and G. Karakonstantis, \"Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation,\" in Proc. of the 21st International Symposium on Quality Electronic Design (ISQED), pp. 225--230, 2020."},{"key":"e_1_3_2_1_19_1","volume-title":"Nov. 17","author":"Accessed ASU","year":"2023","unstructured":"ASU - ASAP7 PDK. Accessed: Nov. 17, 2023. [Online]. Available: https:\/\/github.com\/The-OpenROAD-Project\/asap7\/"}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA","acronym":"DAC '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657351","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3657351","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:18:00Z","timestamp":1750295880000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657351"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":18,"alternative-id":["10.1145\/3649329.3657351","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3657351","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}