{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,15]],"date-time":"2026-05-15T00:03:21Z","timestamp":1778803401700,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"NSFC","award":["62090024"],"award-info":[{"award-number":["62090024"]}]},{"name":"NSFC","award":["62222411"],"award-info":[{"award-number":["62222411"]}]},{"name":"NSFC","award":["62025404"],"award-info":[{"award-number":["62025404"]}]},{"name":"NSFC","award":["92373206"],"award-info":[{"award-number":["92373206"]}]},{"name":"NSFC","award":["62202453"],"award-info":[{"award-number":["62202453"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3657356","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":52,"title":["Data is all you need:  Finetuning LLMs for Chip Design via an Automated design-data augmentation framework"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1920-0101","authenticated-orcid":false,"given":"Kaiyan","family":"Chang","sequence":"first","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing; University of Chinese Academy of Sciences, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-3273-2271","authenticated-orcid":false,"given":"Kun","family":"Wang","sequence":"additional","affiliation":[{"name":"Hangzhou Institute for Advanced Study; Institute of Computing Technology, Chinese Academy of Science, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-8242-5895","authenticated-orcid":false,"given":"Nan","family":"Yang","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Science; University of Chinese Academy of Science, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5172-4736","authenticated-orcid":false,"given":"Ying","family":"Wang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-9107-8764","authenticated-orcid":false,"given":"Dantong","family":"Jin","sequence":"additional","affiliation":[{"name":"Zhejiang Lab, Hangzhou, Zhejiang, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9237-559X","authenticated-orcid":false,"given":"Wenlong","family":"Zhu","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Science; University of Chinese Academy of Science, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-7039-7707","authenticated-orcid":false,"given":"Zhirong","family":"Chen","sequence":"additional","affiliation":[{"name":"Zhejiang University; University of Illinois at Urbana Champaign, Hangzhou, Zhejiang, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7193-464X","authenticated-orcid":false,"given":"Cangyuan","family":"Li","sequence":"additional","affiliation":[{"name":"ICT, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-6432-4385","authenticated-orcid":false,"given":"Hao","family":"Yan","sequence":"additional","affiliation":[{"name":"Shanghai Innovation Center for Processor Technologies; Shanghai University, Shanghai, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5158-7417","authenticated-orcid":false,"given":"Yunhao","family":"Zhou","sequence":"additional","affiliation":[{"name":"Shanghai Innovation Center for Processor Technologies; Shanghai Jiao Tong University, Shanghai, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6252-2160","authenticated-orcid":false,"given":"Zhuoliang","family":"Zhao","sequence":"additional","affiliation":[{"name":"Shanghai Innovation Center for Processor Technologies; FuDan University, Shanghai, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-7591-0418","authenticated-orcid":false,"given":"Yuan","family":"Cheng","sequence":"additional","affiliation":[{"name":"Shanghai Innovation Center for Processor Technologies; Nanjing University, Shanghai, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-0012-4113","authenticated-orcid":false,"given":"Yudong","family":"Pan","sequence":"additional","affiliation":[{"name":"Research Center for Intelligent Computing Systems, Institute of Computing Technology, Chinese Academy of Science, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-8717-068X","authenticated-orcid":false,"given":"Yiqi","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Science; University of Chinese Academy of Science, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7012-2308","authenticated-orcid":false,"given":"Mengdi","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8407-2594","authenticated-orcid":false,"given":"Shengwen","family":"Liang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing; University of Chinese Academy of Sciences, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5113-8067","authenticated-orcid":false,"given":"Yinhe","family":"Han","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology,Chinese Academy of Sciences, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8082-4218","authenticated-orcid":false,"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0874-814X","authenticated-orcid":false,"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"ICT, Chinese Academy of Sciences, Beijing, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"D. Hernandez J. Kaplan T. Henighan and S. McCandlish \"Scaling laws for transfer \" arXiv preprint arXiv:2102.01293 2021."},{"key":"e_1_3_2_1_2_1","first-page":"1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE)","author":"Thakur S.","year":"2023","unstructured":"S. Thakur, B. Ahmad, Z. Fan, H. Pearce, B. Tan, R. Karri, B. Dolan-Gavitt, and S. Garg, \"Benchmarking large language models for automated verilog rtl code generation,\" in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1--6, IEEE, 2023."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430634"},{"key":"e_1_3_2_1_4_1","volume-title":"Chipgpt: How far are we from natural language hardware design,\" arXiv preprint arXiv:2305.14019","author":"Chang K.","year":"2023","unstructured":"K. Chang, Y. Wang, H. Ren, M. Wang, S. Liang, Y. Han, H. Li, and X. Li, \"Chipgpt: How far are we from natural language hardware design,\" arXiv preprint arXiv:2305.14019, 2023."},{"key":"e_1_3_2_1_5_1","volume-title":"Chateda: A large language model powered autonomous agent for eda,\" arXiv preprint arXiv:2308.10204","author":"He Z.","year":"2023","unstructured":"Z. He, H. Wu, X. Zhang, X. Yao, S. Zheng, H. Zheng, and B. Yu, \"Chateda: A large language model powered autonomous agent for eda,\" arXiv preprint arXiv:2308.10204, 2023."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52733.2024.01428"},{"key":"e_1_3_2_1_7_1","first-page":"7554","volume-title":"Adapt: Action-aware driving caption transformer,\" in 2023 IEEE International Conference on Robotics and Automation (ICRA)","author":"Jin B.","year":"2023","unstructured":"B. Jin, X. Liu, Y. Zheng, P. Li, H. Zhao, T. Zhang, Y. Zheng, G. Zhou, and J. Liu, \"Adapt: Action-aware driving caption transformer,\" in 2023 IEEE International Conference on Robotics and Automation (ICRA), pp. 7554--7561, 2023."},{"key":"e_1_3_2_1_8_1","volume-title":"Domain-adapted llms for chip design,\" arXiv preprint arXiv:2307.09288","author":"Mingjie Liu\u00a7 T. E.","year":"2023","unstructured":"T. E. Mingjie Liu\u00a7, \"Chipnemo: Domain-adapted llms for chip design,\" arXiv preprint arXiv:2307.09288, 2023."},{"key":"e_1_3_2_1_9_1","volume-title":"Verigen: A large language model for verilog code generation,\" arXiv preprint arXiv:2308.00708","author":"Thakur S.","year":"2023","unstructured":"S. Thakur, B. Ahmad, H. Pearce, B. Tan, B. Dolan-Gavitt, R. Karri, and S. Garg, \"Verigen: A large language model for verilog code generation,\" arXiv preprint arXiv:2308.00708, 2023."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530673"},{"key":"e_1_3_2_1_11_1","volume-title":"Rtllm: An open-source benchmark for design rtl generation with large language model,\" in Asia and South Pacific Design Automation Conference(ASP-DAC)","author":"Lu Y.","year":"2023","unstructured":"Y. Lu, S. Liu, Q. Zhang, and Z. Xie, \"Rtllm: An open-source benchmark for design rtl generation with large language model,\" in Asia and South Pacific Design Automation Conference(ASP-DAC), 2023."},{"key":"e_1_3_2_1_12_1","volume-title":"VerilogEval: evaluating large language models for verilog code generation,\" in 2023 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Liu M.","year":"2023","unstructured":"M. Liu, N. Pinckney, B. Khailany, and H. Ren, \"VerilogEval: evaluating large language models for verilog code generation,\" in 2023 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2023."},{"key":"e_1_3_2_1_13_1","volume-title":"Chip-chat: Challenges and opportunities in conversational hardware design,\" arXiv preprint arXiv:2305.13243","author":"Blocklove J.","year":"2023","unstructured":"J. Blocklove, S. Garg, R. Karri, and H. Pearce, \"Chip-chat: Challenges and opportunities in conversational hardware design,\" arXiv preprint arXiv:2305.13243, 2023."},{"key":"e_1_3_2_1_14_1","volume-title":"Unleashing the potential of llms for quantum computing: A study in quantum architecture design,\" arXiv preprint arXiv:2307.08191","author":"Liang Z.","year":"2023","unstructured":"Z. Liang, J. Cheng, R. Yang, H. Ren, Z. Song, D. Wu, X. Qian, T. Li, and Y. Shi, \"Unleashing the potential of llms for quantum computing: A study in quantum architecture design,\" arXiv preprint arXiv:2307.08191, 2023."},{"key":"e_1_3_2_1_15_1","volume-title":"On the viability of using llms for sw\/hw co-design: An example in designing cim dnn accelerators,\" arXiv preprint arXiv:2306.06923","author":"Yan Z.","year":"2023","unstructured":"Z. Yan, Y. Qin, X. S. Hu, and Y. Shi, \"On the viability of using llms for sw\/hw co-design: An example in designing cim dnn accelerators,\" arXiv preprint arXiv:2306.06923, 2023."},{"key":"e_1_3_2_1_16_1","volume-title":"Fixing hardware security bugs with large language models,\" arXiv preprint arXiv:2302.01215","author":"Ahmad B.","year":"2023","unstructured":"B. Ahmad, S. Thakur, B. Tan, R. Karri, and H. Pearce, \"Fixing hardware security bugs with large language models,\" arXiv preprint arXiv:2302.01215, 2023."},{"key":"e_1_3_2_1_17_1","volume-title":"Llm-assisted generation of hardware assertions,\" arXiv preprint arXiv:2306.14027","author":"Kande R.","year":"2023","unstructured":"R. Kande, H. Pearce, B. Tan, B. Dolan-Gavitt, S. Thakur, R. Karri, and J. Rajendran, \"Llm-assisted generation of hardware assertions,\" arXiv preprint arXiv:2306.14027, 2023."},{"key":"e_1_3_2_1_18_1","volume-title":"From rtl to sva: Llm-assisted generation of formal verification testbenches","author":"Orenes-Vera M.","year":"2023","unstructured":"M. Orenes-Vera, M. Martonosi, and D. Wentzlaff, \"From rtl to sva: Llm-assisted generation of formal verification testbenches,\" 2023."},{"key":"e_1_3_2_1_19_1","volume-title":"Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models,\" in 2023 IEEE\/ACM International Conference on Computer-AidedDesign (ICCAD)","author":"Fu Y.","year":"2023","unstructured":"Y. Fu, Y. Zhang, Z. Yu, S. Li, Z. Ye, C. Li, C. Wan, and Y. Lin, \"Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models,\" in 2023 IEEE\/ACM International Conference on Computer-AidedDesign (ICCAD), 2023."},{"key":"e_1_3_2_1_20_1","first-page":"196","volume-title":"A paradigm shift or rather a complementary approach?,\" in 2022 8th International Conference on Information Technology Trends (ITT)","author":"Hamid O. H.","year":"2022","unstructured":"O. H. Hamid, \"From model-centric to data-centric ai: A paradigm shift or rather a complementary approach?,\" in 2022 8th International Conference on Information Technology Trends (ITT), pp. 196--199, IEEE, 2022."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jss.2022.111304"},{"key":"e_1_3_2_1_22_1","volume-title":"Fine-tuning pretrained language models: Weight initializations, data orders, and early stopping,\" arXiv preprint arXiv:2002.06305","author":"Dodge J.","year":"2020","unstructured":"J. Dodge, G. Ilharco, R. Schwartz, A. Farhadi, H. Hajishirzi, and N. Smith, \"Fine-tuning pretrained language models: Weight initializations, data orders, and early stopping,\" arXiv preprint arXiv:2002.06305, 2020."},{"key":"e_1_3_2_1_23_1","volume-title":"LoRA: Low-rank adaptation of large language models,\" in International Conference on Learning Representations(ICLR)","author":"Hu E. J.","year":"2022","unstructured":"E. J. Hu, Y. Shen, P. Wallis, Z. Allen-Zhu, Y. Li, S. Wang, L. Wang, and W. Chen, \"LoRA: Low-rank adaptation of large language models,\" in International Conference on Learning Representations(ICLR), 2022."},{"key":"e_1_3_2_1_24_1","first-page":"09288","article-title":"Llama 2: Open foundation and fine-tuned chat models","volume":"2307","author":"Touvron H.","year":"2023","unstructured":"H. Touvron, L. Martin, K. R. Stone, P. Albert, A. Almahairi, Y. Babaei, N. Bashlykov, S. Batra, P. Bhargava, S. Bhosale, D. M. Bikel, L. Blecher, C. C. Ferrer, M. Chen, G. Cucurull, D. Esiobu, J. Fernandes, J. Fu, W. Fu, B. Fuller, C. Gao, V. Goswami, N. Goyal, A. S. Hartshorn, S. Hosseini, R. Hou, H. Inan, M. Kardas, V. Kerkez, M. Khabsa, I. M. Kloumann, A. V. Korenev, P. S. Koura, M.-A. Lachaux, T. Lavril, J. Lee, D. Liskovich, Y. Lu, Y. Mao, X. Martinet, T. Mihaylov, P. Mishra, I. Molybog, Y. Nie, A. Poulton, J. Reizenstein, R. Rungta, K. Saladi, A. Schelten, R. Silva, E. M. Smith, R. Subramanian, X. Tan, B. Tang, R. Taylor, A. Williams, J. X. Kuan, P. Xu, Z. Yan, I. Zarov, Y. Zhang, A. Fan, M. Kambadur, S. Narang, A. Rodriguez, R. Stojnic, S. Edunov, and T. Scialom, \"Llama 2: Open foundation and fine-tuned chat models,\" ArXiv, vol. abs\/2307.09288, 2023.","journal-title":"ArXiv"}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA","acronym":"DAC '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657356","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3657356","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:18:00Z","timestamp":1750295880000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657356"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":24,"alternative-id":["10.1145\/3649329.3657356","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3657356","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}