{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T16:12:24Z","timestamp":1772727144848,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3657369","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-0836-9424","authenticated-orcid":false,"given":"Mingxuan","family":"Li","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-4866-7213","authenticated-orcid":false,"given":"Qinzhe","family":"Zhi","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-5321-8297","authenticated-orcid":false,"given":"Yanchi","family":"Dong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0599-7762","authenticated-orcid":false,"given":"Le","family":"Ye","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China"},{"name":"Advanced Institute of Information Technology of Peking University, Hangzhou, Zhejiang, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4570-4613","authenticated-orcid":false,"given":"Tianyu","family":"Jia","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Annual Conference on Neural Information Processing Systems (NeurIPS)","author":"Lin J.","year":"2022","unstructured":"J. Lin et al., \"On-device training under 256kb memory,\" in Annual Conference on Neural Information Processing Systems (NeurIPS), 2022."},{"key":"e_1_3_2_1_2_1","volume-title":"CFU playground: Full-stack open-source framework for tiny machine learning (tinyml) acceleration on fpgas,\" in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Prakash S.","year":"2023","unstructured":"S. Prakash et al., \"CFU playground: Full-stack open-source framework for tiny machine learning (tinyml) acceleration on fpgas,\" in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2023."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"e_1_3_2_1_4_1","volume-title":"ProxylessNAS: Direct neural architecture search on target task and hardware,\" in International Conference on Learning Representations (ICLR)","author":"Cai H.","year":"2019","unstructured":"H. Cai et al., \"ProxylessNAS: Direct neural architecture search on target task and hardware,\" in International Conference on Learning Representations (ICLR), 2019."},{"key":"e_1_3_2_1_5_1","volume-title":"To prune, or not to prune: exploring the efficacy of pruning for model compression,\" arXiv preprint arXiv:1710.01878","author":"Zhu M.","year":"2017","unstructured":"M. Zhu et al., \"To prune, or not to prune: exploring the efficacy of pruning for model compression,\" arXiv preprint arXiv:1710.01878, 2017."},{"key":"e_1_3_2_1_6_1","volume-title":"Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks,\" in IEEE\/ACM Design Automation Conference (DAC)","author":"Yang L.","year":"2020","unstructured":"L. Yang et al., \"Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks,\" in IEEE\/ACM Design Automation Conference (DAC), 2020."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"D. Rossi et al. \"4.4 a 1.3tops\/w @ 32gops fully integrated 10-core soc for iot end-nodes with 1.7w cognitive wake-up from mram-based state-retentive sleep mode \" in 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 60--61 2021.","DOI":"10.1109\/ISSCC42613.2021.9365939"},{"key":"e_1_3_2_1_8_1","volume-title":"Mobilenetv2: Inverted residuals and linear bottlenecks,\" in IEEE Conference on Computer Vision and Pattern Recognition (CVPR)","author":"Sandler M.","year":"2018","unstructured":"M. Sandler et al., \"Mobilenetv2: Inverted residuals and linear bottlenecks,\" in IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2018."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TKDE.2009.191"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3298981"},{"key":"e_1_3_2_1_11_1","first-page":"142","volume-title":"7.7 LNPU: A 25.3 tflops\/w sparse deep-neural-network learning processor with fine-grained mixed precision of fp8-fp16,\" in IEEE International Solid-State Circuits Conference (ISSCC)","author":"Lee J.","year":"2019","unstructured":"J. Lee et al., \"7.7 LNPU: A 25.3 tflops\/w sparse deep-neural-network learning processor with fine-grained mixed precision of fp8-fp16,\" in IEEE International Solid-State Circuits Conference (ISSCC), pp. 142--144, IEEE, 2019."},{"key":"e_1_3_2_1_12_1","first-page":"140","volume-title":"7.4 GANPU: A 135tflops\/w multi-dnn training processor for gans with speculative dual-sparsity exploitation,\" in IEEE International Solid-State Circuits Conference (ISSCC)","author":"Kang S.","year":"2020","unstructured":"S. Kang et al., \"7.4 GANPU: A 135tflops\/w multi-dnn training processor for gans with speculative dual-sparsity exploitation,\" in IEEE International Solid-State Circuits Conference (ISSCC), pp. 140--142, IEEE, 2020."},{"key":"e_1_3_2_1_13_1","volume-title":"CPE: An energy-efficient edge-device training with multidimensional compression mechanism,\" in IEEE\/ACM Design Automation Conference (DAC)","author":"Wang Z.","year":"2023","unstructured":"Z. Wang et al., \"CPE: An energy-efficient edge-device training with multidimensional compression mechanism,\" in IEEE\/ACM Design Automation Conference (DAC), 2023."},{"key":"e_1_3_2_1_14_1","volume-title":"Novia: A framework for discovering non-conventional inline accelerators,\" in International Symposium on Microarchitecture (MICRO)","author":"Trilla D.","year":"2021","unstructured":"D. Trilla et al., \"Novia: A framework for discovering non-conventional inline accelerators,\" in International Symposium on Microarchitecture (MICRO), 2021."},{"key":"e_1_3_2_1_15_1","volume-title":"Blueface: Integrating an accelerator into the core's pipeline through algorithm-interface co-design for real-time socs,\" in IEEE\/ACM Design Automation Conference (DAC)","author":"Jiang Z.","year":"2023","unstructured":"Z. Jiang et al., \"Blueface: Integrating an accelerator into the core's pipeline through algorithm-interface co-design for real-time socs,\" in IEEE\/ACM Design Automation Conference (DAC), 2023."},{"key":"e_1_3_2_1_16_1","volume-title":"PMLR","author":"Evci U.","year":"2020","unstructured":"U. Evci et al., \"Rigging the lottery: Making all tickets winners,\" in International Conference on Machine Learning (ICML), pp. 2943--2952, PMLR, 2020."}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA","acronym":"DAC '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657369","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3657369","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:18:01Z","timestamp":1750295881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657369"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":16,"alternative-id":["10.1145\/3649329.3657369","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3657369","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}