{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T15:28:50Z","timestamp":1780500530921,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T00:00:00Z","timestamp":1719100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,23]]},"DOI":"10.1145\/3649329.3657370","type":"proceedings-article","created":{"date-parts":[[2024,11,7]],"date-time":"2024-11-07T19:27:22Z","timestamp":1731007642000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-8401-5884","authenticated-orcid":false,"given":"Yan-Jen","family":"Chen","sequence":"first","affiliation":[{"name":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-8105-3748","authenticated-orcid":false,"given":"Cheng-Hsiu","family":"Hsieh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-4222-3933","authenticated-orcid":false,"given":"Po-Han","family":"Su","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-1940-7000","authenticated-orcid":false,"given":"Shao-Hsiang","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0564-5719","authenticated-orcid":false,"given":"Yao-Wen","family":"Chang","sequence":"additional","affiliation":[{"name":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, Taiwan"},{"name":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,11,7]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Virtual Event","author":"Wuu J.","year":"2022","unstructured":"J. Wuu, R. Agarwal, M. Ciraula, C. Dietz, B. Johnson, D. Johnson, R. Schreiber, R. Swaminathan, W. Walker, and S. Naffziger, \"3D V-cache: the implementation of a hybrid-bonded 64MB stacked cache for a 7nm x86-64 CPU,\" in Proceedings of IEEE International Solid-State Circuits Conference, Virtual Event, February 2022."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"W. Gomes S. Khushu D. B. Ingerly P. N. Stover N. I. Chowdhury F. O'Mahony A. Balankutty N. Dolev M. G. Dixon L. Jiang et al. \"8.1 Lakefield and mobility compute: A 3D stacked 10nm and 22FFL hybrid processor system in 12\u00d7 12mm 2 1mm package-on-package \" in Proceedings of IEEE International Solid-State Circuits Conference San Francisco California February 2020.","DOI":"10.1109\/ISSCC19947.2020.9062957"},{"key":"e_1_3_2_1_3_1","unstructured":"TSMC \"The chronicle of CoWoS.\" [Online]. Available: https:\/\/3dfabric.tsmc.com\/english\/dedicatedFoundry\/technology\/cowos.htm"},{"key":"e_1_3_2_1_4_1","volume-title":"Micro-bumping, hybrid bonding, or monolithic? a PPA study for heterogeneous 3D IC options,\" in Proceedings of ACM\/IEEE Design Automation Conference","author":"Kim J.","year":"2021","unstructured":"J. Kim, L. Zhu, H. M. Torun, M. Swaminathan, and S. K. Lim, \"Micro-bumping, hybrid bonding, or monolithic? a PPA study for heterogeneous 3D IC options,\" in Proceedings of ACM\/IEEE Design Automation Conference, San Francisco, California, December 2021."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2952542"},{"key":"e_1_3_2_1_6_1","volume-title":"Virtual Event","author":"Vanna-Iampikul P.","year":"2021","unstructured":"P. Vanna-Iampikul, C. Shao, Y.-C. Lu, S. Pentapati, and S. K. Lim, \"Snap-3D: A constrained placement-driven physical design methodology for face-to-face-bonded 3D ICs,\" in Proceedings of International Symposium on Physical Design, Virtual Event, March 2021."},{"key":"e_1_3_2_1_7_1","volume-title":"TP-GNN: A graph neural network framework for tier partitioning in monolithic 3D ICs,\" in Proceedings of ACM\/IEEE Design Automation Conference","author":"Lu Y.-C.","year":"2020","unstructured":"Y.-C. Lu, S. S. Kiran Pentapati, L. Zhu, K. Samadi, and S. K. Lim, \"TP-GNN: A graph neural network framework for tier partitioning in monolithic 3D ICs,\" in Proceedings of ACM\/IEEE Design Automation Conference, San Francisco, California, July 2020."},{"key":"e_1_3_2_1_8_1","volume-title":"iPL-3D: A novel bilevel programming model for die-to-die placement,\" in Proceedings of IEEE\/ACM International Conference on Computer-Aided Design","author":"Zhao X.","year":"2023","unstructured":"X. Zhao, S. Chen, Y. Qiu, J. Li, Z. Huang, B. Xie, X. Li, and Y. Bao, \"iPL-3D: A novel bilevel programming model for die-to-die placement,\" in Proceedings of IEEE\/ACM International Conference on Computer-Aided Design, San Francisco, California, October\/November 2023."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2226584"},{"key":"e_1_3_2_1_10_1","volume-title":"Santa Rosa","author":"Lu J.","year":"2016","unstructured":"J. Lu, H. Zhuang, I. Kang, P. Chen, and C.-K. Cheng, \"ePlace-3D: Electrostatics based placement for 3D-ICs,\" in Proceedings of International Symposium on Physical Design, Santa Rosa, California, April 2016."},{"key":"e_1_3_2_1_11_1","volume-title":"Analytical placement for 3D ICs with multiple manufacturing technologies,\" in Proceedings of ACM\/IEEE Design Automation Conference","author":"Chen Y.-J.","year":"2023","unstructured":"Y.-J. Chen, Y.-S. Chen, W.-C. Tseng, C.-Y. Chiang, Y.-H. Lo, and Y.-W. Chang, \"Late breaking results: Analytical placement for 3D ICs with multiple manufacturing technologies,\" in Proceedings of ACM\/IEEE Design Automation Conference, San Francisco, California, July 2023."},{"key":"e_1_3_2_1_12_1","volume-title":"Analytical die-to-die 3D placement with bistratal wirelength model and GPU acceleration,\" arXiv preprint arXiv:2310.07424","author":"Liao P.","year":"2023","unstructured":"P. Liao, Y. Zhao, D. Guo, Y. Lin, and B. Yu, \"Analytical die-to-die 3D placement with bistratal wirelength model and GPU acceleration,\" arXiv preprint arXiv:2310.07424, 2023."},{"key":"e_1_3_2_1_13_1","volume-title":"3D placement with macros,\" in Proceedings of IEEE\/ACM International Conference on Computer-Aided Design","author":"Hu K.-S.","year":"2023","unstructured":"K.-S. Hu, H.-Y. Chi, I.-J. Lin, Y.-H. Wu, W.-H. Chen, and Y.-T. Hsieh, \"2023 ICCAD CAD contest problem B: 3D placement with macros,\" in Proceedings of IEEE\/ACM International Conference on Computer-Aided Design, San Francisco, California, October\/November 2023."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2391263"},{"key":"e_1_3_2_1_15_1","unstructured":"H.-C. Chen Y.-L. Chuang Y.-W. Chang and Y.-C. Chang \"Constraint graph-based macro placement for modern mixed-size circuit designs \" in Proceedings of IEEE\/ACM International Conference on Computer-Aided Design San Jose California November 2008."},{"key":"e_1_3_2_1_16_1","volume-title":"Portland","author":"Spindler P.","year":"2008","unstructured":"P. Spindler, U. Schlichtmann, and F. M. Johannes, \"Abacus: Fast legalization of standard cell circuits with minimal movement,\" in Proceedings of International Symposium on Physical Design, Portland, Oregon, April 2008."},{"key":"e_1_3_2_1_17_1","unstructured":"D. Hill \"Method and system for high speed detailed placement of cells within an integrated circuit design \" Apr. 9 2002 U.S. Patent 6 370 673."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"e_1_3_2_1_19_1","volume-title":"A hybrid placer using partitioning and analytical techniques,\" in Proceedings of International Symposium on Physical Design","author":"Jiang Z.-W.","year":"2006","unstructured":"Z.-W. Jiang, T.-C. Cheny, T.-C. Hsuy, H.-C. Chenz, and Y.-W. Chang, \"NTUplace2: A hybrid placer using partitioning and analytical techniques,\" in Proceedings of International Symposium on Physical Design, San Jose, California, April 2006."}],"event":{"name":"DAC '24: 61st ACM\/IEEE Design Automation Conference","location":"San Francisco CA USA","acronym":"DAC '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 61st ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657370","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649329.3657370","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:18:01Z","timestamp":1750295881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649329.3657370"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,23]]},"references-count":19,"alternative-id":["10.1145\/3649329.3657370","10.1145\/3649329"],"URL":"https:\/\/doi.org\/10.1145\/3649329.3657370","relation":{},"subject":[],"published":{"date-parts":[[2024,6,23]]},"assertion":[{"value":"2024-11-07","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}