{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,8]],"date-time":"2026-07-08T16:58:28Z","timestamp":1783529908283,"version":"3.55.0"},"reference-count":68,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2024,5,21]],"date-time":"2024-05-21T00:00:00Z","timestamp":1716249600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"crossref","award":["2019YFB2204800"],"award-info":[{"award-number":["2019YFB2204800"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2024,6,30]]},"abstract":"<jats:p>DRAM memory is a performance bottleneck for many applications, due to its high access latency. Previous work has mainly focused on data locality, introducing small but fast regions to cache frequently accessed data, thereby reducing the average latency. However, these locality-based designs have three challenges in modern multi-core systems: (1) inter-application interference leads to random memory access traffic, (2) fairness issues prevent the memory controller from over-prioritizing data locality, and (3) write-intensive applications have much lower locality and evict substantial dirty entries. With frequent data movement between the fast in-DRAM cache and slow regular arrays, the overhead induced by moving data may even offset the performance and energy benefits of in-DRAM caching.<\/jats:p>\n          <jats:p>In this article, we decouple the data movement process into two distinct phases. The first phase is Load-Reduced Destructive Activation (LRDA), which destructively promotes data into the in-DRAM cache. The second phase is Delayed Cycle-Stealing Restoration (DCSR), which restores the original data when the DRAM bank is idle. LRDA decouples the most time-consuming restoration phase from activation, and DCSR hides the restoration latency through prevalent bank-level parallelism. We propose FASA-DRAM, incorporating destructive activation and delayed restoration techniques to enable both in-DRAM caching and proactive latency-hiding mechanisms. Our evaluation shows that FASA-DRAM improves the average performance by 19.9% and reduces average DRAM energy consumption by 18.1% over DDR4 DRAM for four-core workloads, with less than 3.4% extra area overhead. Furthermore, FASA-DRAM outperforms state-of-the-art designs in both performance and energy efficiency.<\/jats:p>","DOI":"10.1145\/3649455","type":"journal-article","created":{"date-parts":[[2024,5,21]],"date-time":"2024-05-21T12:09:32Z","timestamp":1716293372000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration"],"prefix":"10.1145","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4203-6381","authenticated-orcid":false,"given":"Haitao","family":"Du","sequence":"first","affiliation":[{"name":"University of Science and Technology of China, Hefei, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-9179-938X","authenticated-orcid":false,"given":"Yuhan","family":"Qin","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, Hefei, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0341-3428","authenticated-orcid":false,"given":"Song","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, Hefei, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5487-6855","authenticated-orcid":false,"given":"Yi","family":"Kang","sequence":"additional","affiliation":[{"name":"University of Science and Technology of China, Hefei, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,5,21]]},"reference":[{"key":"e_1_3_2_2_2","volume-title":"42nd Annual International Symposium on Computer Architecture","year":"2015","unstructured":"Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, and Bruce Jacob. 2015. Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions. In 42nd Annual International Symposium on Computer Architecture."},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_4_2","first-page":"316","volume-title":"Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems","year":"2018","unstructured":"Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, and Onur Mutlu. 2018. Google workloads for consumer devices: Mitigating data movement bottlenecks. In Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems. 316\u2013331."},{"key":"e_1_3_2_5_2","volume-title":"2022 IEEE International Symposium on High Performance Computer Architecture","year":"2022","unstructured":"F. Nisa Bostanc\u0131, Ataberk Olgun, Lois Orosa, A. Giray Ya\u01e7l\u0131k\u00e7\u0131, Jeremie S. Kim, Hasan Hassan, O\u01e7uz Ergin, and Onur Mutlu. 2022. DR-STRaNGe: End-to-end system design for DRAM-based true random number generators. In 2022 IEEE International Symposium on High Performance Computer Architecture. IEEE."},{"key":"e_1_3_2_6_2","volume-title":"2016 IEEE International Symposium on High Performance Computer Architecture","year":"2016","unstructured":"Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, and Onur Mutlu. 2016. Low-cost inter-linked subarrays (LISA): Enabling fast inter-subarray data movement in DRAM. In 2016 IEEE International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_2_7_2","volume-title":"2014 IEEE International Symposium on High Performance Computer Architecture (HPCA\u201914)","year":"2014","unstructured":"Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, and Onur Mutlu. 2014. Improving DRAM performance by parallelizing refreshes with accesses. In 2014 IEEE International Symposium on High Performance Computer Architecture (HPCA\u201914)."},{"key":"e_1_3_2_8_2","first-page":"73","volume-title":"2017 IEEE International Symposium on High Performance Computer Architecture (HPCA\u201917)","year":"2017","unstructured":"Niladrish Chatterjee, Mike O\u2019Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, and William J. Dally. 2017. Architecting an energy-efficient dram system for GPUs. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA\u201917). IEEE, 73\u201384."},{"key":"e_1_3_2_9_2","first-page":"223","volume-title":"2015 ACM\/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA\u201915)","year":"2015","unstructured":"Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, and Lee-Sup Kim. 2015. Multiple clone row DRAM: A low latency and area optimized DRAM. In 2015 ACM\/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA\u201915). IEEE, 223\u2013234."},{"key":"e_1_3_2_10_2","unstructured":"Standard Performance Evaluation Corporation. 2017. SPEC CPU 2017. https:\/\/www.spec.org\/cpu2017\/"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/1735971.1736058"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"e_1_3_2_13_2","doi-asserted-by":"crossref","unstructured":"Saugata Ghose Tianshi Li Nastaran Hajinazar Damla Senol Cali and Onur Mutlu. 2019. Demystifying complex workload-dram interactions: An experimental study. ACM on Measurement and Analysis of Computing Systems 3 3 (2019) 1\u201350.","DOI":"10.1145\/3366708"},{"key":"e_1_3_2_14_2","unstructured":"Arizona State University NIMO Group. 2006. Predictive Technology Model. http:\/\/ptm.asu.edu\/"},{"key":"e_1_3_2_15_2","unstructured":"SAFARI Research Group. 2020. CLR-DRAM SPICE Model. https:\/\/github.com\/CMU-SAFARI\/clrdram"},{"issue":"4","key":"e_1_3_2_16_2","first-page":"1","article-title":"Simpoint 3.0: Faster and more flexible program phase analysis","volume":"7","author":"Hamerly Greg","year":"2005","unstructured":"Greg Hamerly, Erez Perelman, Jeremy Lau, and Brad Calder. 2005. Simpoint 3.0: Faster and more flexible program phase analysis. Journal of Instruction Level Parallelism 7, 4 (2005), 1\u201328.","journal-title":"Journal of Instruction Level Parallelism"},{"key":"e_1_3_2_17_2","doi-asserted-by":"crossref","unstructured":"Hasan Hassan Minesh Patel Jeremie S. Kim A. Giray Yaglikci Nandita Vijaykumar Nika Mansouri Ghiasi Saugata Ghose and Onur Mutlu. 2019. CROW: A low-cost substrate for improving dram performance energy efficiency and reliability. In Proceedings of the 46th International Symposium on Computer Architecture. 129\u2013142.","DOI":"10.1145\/3307650.3322231"},{"key":"e_1_3_2_18_2","volume-title":"2016 IEEE International Symposium on High Performance Computer Architecture","year":"2016","unstructured":"Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, and Onur Mutlu. 2016. ChargeCache: Reducing DRAM latency by exploiting row access locality. In 2016 IEEE International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/3446200"},{"key":"e_1_3_2_20_2","volume-title":"Memory Systems: Cache, DRAM, Disk","author":"Jacob Bruce","year":"2010","unstructured":"Bruce Jacob, David Wang, and Spencer Ng. 2010. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann."},{"key":"e_1_3_2_21_2","unstructured":"JEDEC. 2013. DDR4 SDRAM STANDARD JESD79-4A."},{"key":"e_1_3_2_22_2","unstructured":"JEDEC. 2021. DDR5 SDRAM STANDARD JESD79-5A."},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/9780470544426"},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926262"},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/4.701271"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00060"},{"key":"e_1_3_2_28_2","doi-asserted-by":"crossref","unstructured":"Yoongu Kim Ross Daly Jeremie Kim Chris Fallin Ji Hye Lee Donghyuk Lee Chris Wilkerson Konrad Lai and Onur Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ACM SIGARCH Computer Architecture News 42 3 (2014) 361\u2013372.","DOI":"10.1145\/2678373.2665726"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337202"},{"key":"e_1_3_2_31_2","first-page":"27","volume-title":"2023 IEEE International Solid-State Circuits Conference (ISSCC\u201923)","year":"2023","unstructured":"Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jungbum Shin, Yanggyoon Loh, Chang Yong Lee, Junmyung Woo, Hyeseung Yu, Changhyun Bae, Reum Oh, Young-soo Sohn, Changsik Yoo, and Jooyoung Lee. 2023. 28.7 A 1.1 V 6.4 Gb\/s\/pin 24-Gb DDR5 SDRAM with a highly-accurate duty corrector and NBTI-Tolerant DLL. In 2023 IEEE International Solid-State Circuits Conference (ISSCC\u201923). IEEE, 27\u201329."},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669155"},{"key":"e_1_3_2_33_2","first-page":"615","volume-title":"2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA\u201913)","year":"2013","unstructured":"Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu. 2013. Tiered-latency DRAM: A low latency and low cost DRAM architecture. In 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA\u201913). IEEE, 615\u2013626."},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.35"},{"key":"e_1_3_2_35_2","volume-title":"42nd Annual IEEE\/ACM International Symposium on Microarchitecture","year":"2009","unstructured":"Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, and Norman P. Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In 42nd Annual IEEE\/ACM International Symposium on Microarchitecture."},{"key":"e_1_3_2_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.2973991"},{"key":"e_1_3_2_37_2","doi-asserted-by":"crossref","unstructured":"Kevin Lim Jichuan Chang Trevor Mudge Parthasarathy Ranganathan Steven K. Reinhardt and Thomas FWenisch. 2009. Disaggregated memory for expansion and sharing in blade servers. ACM SIGARCH Computer Architecture News 37 3 (2009) 267\u2013278.","DOI":"10.1145\/1555815.1555789"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337161"},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830827"},{"key":"e_1_3_2_40_2","first-page":"666","volume-title":"2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920)","year":"2020","unstructured":"Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, A. Giray Ya\u01e7l\u0131k\u00e7\u0131, Lois Orosa, Jisung Park, and Onur Mutlu. 2020. CLR-DRAM: A low-cost DRAM architecture enabling dynamic capacity-latency trade-off. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA\u201920). IEEE, 666\u2013679."},{"key":"e_1_3_2_41_2","volume-title":"44rd IEEE Symposium on Security and Privacy (SP\u201923)","year":"2023","unstructured":"Michele Marazzi, Flavien Solt, Patrick Jattke, Kubo Takashi, and Kaveh Razavi. 2023. REGA: Scalable rowhammer mitigation with refresh-generating activations. In 44rd IEEE Symposium on Security and Privacy (SP\u201923)."},{"key":"e_1_3_2_42_2","volume-title":"Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium","author":"Moscibroda Thomas","year":"2007","unstructured":"Thomas Moscibroda and Onur Mutlu. 2007. Memory performance attacks: Denial of memory service in multi-core systems. In Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium. USENIX Association."},{"key":"e_1_3_2_43_2","volume-title":"44th Annual IEEE\/ACM International Symposium on Microarchitecture","year":"2011","unstructured":"Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda. 2011. Reducing memory interference in multicore systems via application-aware memory channel partitioning. In 44th Annual IEEE\/ACM International Symposium on Microarchitecture."},{"key":"e_1_3_2_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"e_1_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124545"},{"key":"e_1_3_2_46_2","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480069"},{"key":"e_1_3_2_47_2","volume-title":"International Conference on Architectural Support for Programming Languages and Operating Systems","year":"2013","unstructured":"Heekwon Park, Seungjae Baek, Jongmoo Choi, Donghee Lee, and Sam H. Noh. 2013. Regularities considered harmful: Forcing randomness to memory accesses to reduce row buffer conflicts for multi-core, multi-bank systems. In International Conference on Architectural Support for Programming Languages and Operating Systems."},{"key":"e_1_3_2_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"e_1_3_2_49_2","unstructured":"Rambus. 2010. DRAM Power Model. http:\/\/www.rambus.com\/energy\/"},{"key":"e_1_3_2_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00019"},{"key":"e_1_3_2_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853230"},{"key":"e_1_3_2_52_2","volume-title":"Proceedings of the 46th Annual IEEE\/ACM International Symposium on Microarchitecture","year":"2013","unstructured":"Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, and Todd C. Mowry. 2013. RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization. In Proceedings of the 46th Annual IEEE\/ACM International Symposium on Microarchitecture."},{"issue":"7","key":"e_1_3_2_53_2","first-page":"2213","article-title":"Q-DRAM: Quick-access DRAM with decoupled restoring from row-activation","volume":"65","year":"2015","unstructured":"Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Hongsik Kim, and Lee-Sup Kim. 2015. Q-DRAM: Quick-access DRAM with decoupled restoring from row-activation. IEEE Transactions on Computers 65, 7 (2015), 2213\u20132227.","journal-title":"IEEE Transactions on Computers"},{"key":"e_1_3_2_54_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835956"},{"key":"e_1_3_2_55_2","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"e_1_3_2_56_2","volume-title":"40th Annual International Symposium on Computer Architecture","year":"2013","unstructured":"Young Hoon Son, O. Seongil, Yuhwan Ro, Jae W. Lee, and Jung Ho Ahn. 2013. Reducing memory access latency with asymmetric DRAM bank organizations. In 40th Annual International Symposium on Computer Architecture."},{"key":"e_1_3_2_57_2","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196008"},{"key":"e_1_3_2_58_2","doi-asserted-by":"crossref","unstructured":"Daisaburo Takashima Shigeyoshi Watanabe Hiroaki Nakano Yukihito Oowaki and Kazunori Ohuchi. 1994. Open\/folded bit-line arrangement for ultra-high-density DRAM\u2019s. IEICE Transactions on Electronics 29 4 (1994) 539\u2013542.","DOI":"10.1109\/4.280706"},{"key":"e_1_3_2_59_2","unstructured":"Micron Technology. 2015. DDR4 SDRAM Datasheet."},{"key":"e_1_3_2_60_2","unstructured":"Micron Technology. 2017. Calculating Memory Power for DDR4 SDRAM TN-40-07."},{"key":"e_1_3_2_61_2","unstructured":"The Third Data Prefetching Championship (DPC3). 2019. https:\/\/dpc3.compas.cs.stonybrook.edu\/"},{"key":"e_1_3_2_62_2","first-page":"175","volume-title":"37th Annual International Symposium on Computer Architecture","year":"2010","unstructured":"Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Norman P. Jouppi. 2010. Rethinking DRAM design and organization for energy-constrained multi-cores. In 37th Annual International Symposium on Computer Architecture. 175\u2013186."},{"key":"e_1_3_2_63_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"key":"e_1_3_2_64_2","first-page":"313","volume-title":"2020 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201920)","year":"2020","unstructured":"Yaohua Wang, Lois Orosa, Xiangjun Peng, Yang Guo, Saugata Ghose, Minesh Patel, Jeremie S. Kim, Juan G\u00f3mez Luna, Mohammad Sadrosadati, Nika Mansouri Ghiasi, and Onur Mutlu. 2020. Figaro: Improving system performance via fine-grained in-dram data relocation and caching. In 2020 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201920). IEEE, 313\u2013328."},{"key":"e_1_3_2_65_2","volume-title":"2018 51st Annual IEEE\/ACM International Symposium on Microarchitecture","year":"2018","unstructured":"Yaohua Wang, Arash Tavakkol, Lois Orosa, Saugata Ghose, Nika Mansouri Ghiasi, Minesh Patel, Jeremie S. Kim, Hasan Hassan, Mohammad Sadrosadati, and Onur Mutlu. 2018. Reducing DRAM latency via charge-level-aware look-ahead partial restoration. In 2018 51st Annual IEEE\/ACM International Symposium on Microarchitecture. IEEE."},{"key":"e_1_3_2_66_2","doi-asserted-by":"publisher","DOI":"10.5555\/3437539.3437776"},{"key":"e_1_3_2_67_2","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665724"},{"key":"e_1_3_2_68_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446093"},{"key":"e_1_3_2_69_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649455","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649455","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T00:03:16Z","timestamp":1750291396000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649455"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,21]]},"references-count":68,"aliases":["10.1145\/3649135"],"journal-issue":{"issue":"2","published-print":{"date-parts":[[2024,6,30]]}},"alternative-id":["10.1145\/3649455"],"URL":"https:\/\/doi.org\/10.1145\/3649455","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,5,21]]},"assertion":[{"value":"2023-10-29","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-02-05","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-05-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}