{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T02:00:03Z","timestamp":1782352803142,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T00:00:00Z","timestamp":1718150400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"IEEE CEDA Student Travel Grant"},{"DOI":"10.13039\/501100006374","name":"Hellenic Foundation for Research and Innovation","doi-asserted-by":"publisher","award":["9568"],"award-info":[{"award-number":["9568"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,12]]},"DOI":"10.1145\/3649476.3658756","type":"proceedings-article","created":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T12:29:41Z","timestamp":1718022581000},"page":"403-408","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["An Electromigration-Aware Wire Sizing Methodology via Particle Swarm Optimization"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8093-5882","authenticated-orcid":false,"given":"Olympia","family":"Axelou","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, University of Thessaly, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9442-3340","authenticated-orcid":false,"given":"Kostas","family":"Kolomvatsos","sequence":"additional","affiliation":[{"name":"University of Thessaly, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2867-9604","authenticated-orcid":false,"given":"George","family":"Floros","sequence":"additional","affiliation":[{"name":"University of Thessaly, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6968-0222","authenticated-orcid":false,"given":"Nestor","family":"Evmorfopoulos","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering - University of Thessaly, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-4695-4637","authenticated-orcid":false,"given":"Georg","family":"Georgakos","sequence":"additional","affiliation":[{"name":"Infineon Technologies AG, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2032-5094","authenticated-orcid":false,"given":"George","family":"Stamoulis","sequence":"additional","affiliation":[{"name":"University of Thessaly, Greece"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,6,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549476"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1969.16754"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.322842"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2666723"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"E. Chu Y. Luo and P. Gupta. 2020. Design Impacts of Back-End-of-Line Line Edge Roughness. IEEE Transactions on Semiconductor Manufacturing (2020).","DOI":"10.1109\/TSM.2019.2953864"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2800707"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/CEC.2012.6256112"},{"key":"e_1_3_2_1_8_1","volume-title":"Experimental characterization and modeling of the reliability of interconnect trees. Journal of Applied Physics","author":"Hau-Riege P.","year":"2001","unstructured":"S.\u00a0P. Hau-Riege and C.\u00a0V. Thompson. 2001. Experimental characterization and modeling of the reliability of interconnect trees. Journal of Applied Physics (2001)."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593180"},{"key":"e_1_3_2_1_10_1","volume-title":"Proceedings of ICNN\u201995 - International Conference on Neural Networks.","author":"Kennedy J.","unstructured":"J. Kennedy and R. Eberhart. 1995. Particle swarm optimization. In Proceedings of ICNN\u201995 - International Conference on Neural Networks."},{"key":"e_1_3_2_1_11_1","volume-title":"Stress evolution due to electromigration in confined metal lines. Journal of Applied Physics","author":"Korhonen A.","year":"1993","unstructured":"M.\u00a0A. Korhonen, P. Bo\/rgesen, K.\u00a0N. Tu, and Che\u2010Yu Li. 1993. Stress evolution due to electromigration in confined metal lines. Journal of Applied Physics (1993)."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"J. Lienig and M. Thiele. 2018. Fundamentals of electromigration-aware integrated circuit design. Springer International Publishing.","DOI":"10.1007\/978-3-319-73558-0"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPFA.2008.4588207"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"L. Milor and S. Ghosh. 2023. Calibration and efficient evaluation of electromigration lifetime for interconnect wire sizing of multi-port networks. Microelectronics Reliability (2023) 115163.","DOI":"10.1016\/j.microrel.2023.115163"},{"key":"e_1_3_2_1_15_1","volume-title":"Power Grid Fixing for Electromigration-induced Voltage Failures. In 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). 1\u20138.","author":"Moudallal Z.","year":"2019","unstructured":"Z. Moudallal, V. Sukharev, and F.\u00a0N. Najm. 2019. Power Grid Fixing for Electromigration-induced Voltage Failures. In 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). 1\u20138."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/1356802.1356895"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309880"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2206781.2206854"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2889079"}],"event":{"name":"GLSVLSI '24: Great Lakes Symposium on VLSI 2024","location":"Clearwater FL USA","acronym":"GLSVLSI '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2024"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658756","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649476.3658756","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T02:28:53Z","timestamp":1755829733000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658756"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,12]]},"references-count":19,"alternative-id":["10.1145\/3649476.3658756","10.1145\/3649476"],"URL":"https:\/\/doi.org\/10.1145\/3649476.3658756","relation":{},"subject":[],"published":{"date-parts":[[2024,6,12]]},"assertion":[{"value":"2024-06-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}