{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T15:28:38Z","timestamp":1780500518383,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T00:00:00Z","timestamp":1718150400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,12]]},"DOI":"10.1145\/3649476.3658781","type":"proceedings-article","created":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T12:29:41Z","timestamp":1718022581000},"page":"338-342","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3123-4681","authenticated-orcid":false,"given":"Jingzhou","family":"Li","sequence":"first","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-3984-9399","authenticated-orcid":false,"given":"Huaiyu","family":"Chen","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-7607-3682","authenticated-orcid":false,"given":"Wenbin","family":"Zhang","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3239-430X","authenticated-orcid":false,"given":"Hu","family":"He","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,6,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT50435.2020.9250871"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.191981"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"A. Burns S. Punnekkat 1999. Probabilistic scheduling guarantees for fault-tolerant real-time systems. In Dependable Computing for Critical Applications 7. 361\u2013378.","DOI":"10.1109\/DCFTS.1999.814306"},{"key":"e_1_3_2_1_5_1","unstructured":"International\u00a0Organization for Standardization. 2018. ISO\/DIS 26262. Road Vehicles \u2013 Functional Safety."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2434958"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/30350.30353"},{"key":"e_1_3_2_1_8_1","unstructured":"IBM. 2008. PowerPC 750GX Lockstep Facility. Application note."},{"key":"e_1_3_2_1_9_1","unstructured":"Infineon. [n. d.]. AURIX - TriCore datasheet. highly integrated and performance optimized 32-bit microcontrollers for automotive and industrial applications."},{"key":"e_1_3_2_1_10_1","volume-title":"2016 46th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W). 246\u2013249","author":"Iturbe Xabier","year":"2016","unstructured":"Xabier Iturbe, Balaji Venu, Emre Ozer, and Shidhartha Das. 2016. A Triple Core Lock-Step (TCLS) ARM\u00ae Cortex\u00ae-R5 Processor for Safety-Critical and Ultra-Reliable Applications. In 2016 46th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W). 246\u2013249."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976923"},{"key":"e_1_3_2_1_12_1","unstructured":"Dev Pradhan. 2018. Next-Generation Functional Safety Architecture. https:\/\/community.nxp.com\/pwmxy87654\/attachments\/pwmxy87654\/tech-days\/26\/1\/AMF-AUT-T3378.pdf"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339652"},{"key":"e_1_3_2_1_14_1","unstructured":"Freescale Semiconductor. 2012. MPC5566 Microcontroller Reference Manual."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Daniel\u00a0P Siewiorek and Robert\u00a0S Swarz. 1998. Reliable computer systems: design and evaluation. AK Peters\/CRC Press.","DOI":"10.1201\/9781439863961"},{"key":"e_1_3_2_1_16_1","unstructured":"Andrew Waterman and Krste Asanovic. [n. d.]. riscv-spec. https:\/\/riscv.org\/technical\/specifications\/"}],"event":{"name":"GLSVLSI '24: Great Lakes Symposium on VLSI 2024","location":"Clearwater FL USA","acronym":"GLSVLSI '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2024"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658781","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649476.3658781","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T02:30:52Z","timestamp":1755829852000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658781"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,12]]},"references-count":16,"alternative-id":["10.1145\/3649476.3658781","10.1145\/3649476"],"URL":"https:\/\/doi.org\/10.1145\/3649476.3658781","relation":{},"subject":[],"published":{"date-parts":[[2024,6,12]]},"assertion":[{"value":"2024-06-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}