{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:11:38Z","timestamp":1755997898518,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T00:00:00Z","timestamp":1718150400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,12]]},"DOI":"10.1145\/3649476.3658789","type":"proceedings-article","created":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T12:29:41Z","timestamp":1718022581000},"page":"277-281","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7216-8214","authenticated-orcid":false,"given":"Zihan","family":"Yin","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, University of Wisconsin-Madison, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-8261-0589","authenticated-orcid":false,"given":"Annewsha","family":"Datta","sequence":"additional","affiliation":[{"name":"University of Southern California, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7651-760X","authenticated-orcid":false,"given":"Shwetha","family":"Vijayakumar","sequence":"additional","affiliation":[{"name":"University of Southern California, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9830-0604","authenticated-orcid":false,"given":"Ajey","family":"Jacob","sequence":"additional","affiliation":[{"name":"Information Sciences Institute, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9911-2624","authenticated-orcid":false,"given":"Akhilesh","family":"Jaiswal","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,6,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848999"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-023-02481-5"},{"key":"e_1_3_2_1_3_1","first-page":"656","article-title":"High-assurance processor active memory content protection","volume":"8","author":"Furusawa Michael\u00a0Masaji","year":"2014","unstructured":"Michael\u00a0Masaji Furusawa 2014. High-assurance processor active memory content protection. US Patent 8,656,185.","journal-title":"US Patent"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1506409.1506429"},{"key":"e_1_3_2_1_5_1","volume-title":"2014 International Symposium on Integrated Circuits (ISIC). IEEE, 320\u2013323","author":"Ho Weng-Geng","year":"2014","unstructured":"Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph\u00a0S Chang, and Ne\u00a0Kyaw\u00a0Zwa Lwin. 2014. A dynamic-voltage-scaling 1kbyte \u00d7 8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. In 2014 International Symposium on Integrated Circuits (ISIC). IEEE, 320\u2013323."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2927363"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527336"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415678"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415678"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3064189"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2015.7285052"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2980533"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778160"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196089"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2984161"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2005.852523"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2007.4545460"},{"key":"e_1_3_2_1_19_1","first-page":"1733","article-title":"XNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks","volume":"55","author":"Yin Shihui","year":"2020","unstructured":"Shihui Yin, Zhewei Jiang, Jae-Sun Seo, and Mingoo Seok. 2020. XNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks. IEEE Journal of Solid-State Circuits 55, 6 (2020), 1733\u20131743.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.10"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"e_1_3_2_1_22_1","first-page":"1695","article-title":"A 55nm, 0.4 V 5526-TOPS\/W compute-in-memory binarized CNN accelerator for AIoT applications","volume":"68","author":"Zhang Hongtu","year":"2021","unstructured":"Hongtu Zhang, Yuhao Shu, Weixiong Jiang, Zihan Yin, Wenfeng Zhao, and Yajun Ha. 2021. A 55nm, 0.4 V 5526-TOPS\/W compute-in-memory binarized CNN accelerator for AIoT applications. IEEE Transactions on Circuits and Systems II: Express Briefs 68, 5 (2021), 1695\u20131699.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"e_1_3_2_1_24_1","first-page":"3122","article-title":"Event-driven circuits and systems: A promising low power technique for intelligent sensors in aiot era","volume":"69","author":"Zhao Yang","year":"2022","unstructured":"Yang Zhao and Yong Lian. 2022. Event-driven circuits and systems: A promising low power technique for intelligent sensors in aiot era. IEEE Transactions on Circuits and Systems II: Express Briefs 69, 7 (2022), 3122\u20133128.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"}],"event":{"name":"GLSVLSI '24: Great Lakes Symposium on VLSI 2024","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Clearwater FL USA","acronym":"GLSVLSI '24"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2024"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658789","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649476.3658789","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T02:31:23Z","timestamp":1755829883000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658789"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,12]]},"references-count":24,"alternative-id":["10.1145\/3649476.3658789","10.1145\/3649476"],"URL":"https:\/\/doi.org\/10.1145\/3649476.3658789","relation":{},"subject":[],"published":{"date-parts":[[2024,6,12]]},"assertion":[{"value":"2024-06-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}