{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:02:39Z","timestamp":1755907359293,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T00:00:00Z","timestamp":1718150400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,12]]},"DOI":"10.1145\/3649476.3658805","type":"proceedings-article","created":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T12:29:41Z","timestamp":1718022581000},"page":"588-591","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-0568-2137","authenticated-orcid":false,"given":"Rasheed","family":"Almawzan","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, University of Florida, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3146-8496","authenticated-orcid":false,"given":"Atri","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"University of Florida, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0786-9185","authenticated-orcid":false,"given":"Aritra","family":"Dasgupta","sequence":"additional","affiliation":[{"name":"University of Florida, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6082-6961","authenticated-orcid":false,"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[{"name":"University of Florida, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,6,12]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering. IACR Transactions on Cryptographic Hardware and Embedded Systems","author":"Albartus Nils","year":"2020","unstructured":"Nils Albartus, Max Hoffmann, Sebastian Temme, Leonid Azriel, and Christof Paar. 2020. DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering. IACR Transactions on Cryptographic Hardware and Embedded Systems (2020), 309\u2013336."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2018.8607163"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317831"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2015.7102410"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050606"},{"key":"e_1_3_2_1_7_1","volume-title":"Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection","author":"Rahman Md\u00a0Moshiur","year":"2023","unstructured":"Md\u00a0Moshiur Rahman and Swarup Bhunia. 2023. Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2023)."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403631"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511144"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"}],"event":{"name":"GLSVLSI '24: Great Lakes Symposium on VLSI 2024","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Clearwater FL USA","acronym":"GLSVLSI '24"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2024"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658805","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649476.3658805","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T02:29:38Z","timestamp":1755829778000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3658805"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,12]]},"references-count":11,"alternative-id":["10.1145\/3649476.3658805","10.1145\/3649476"],"URL":"https:\/\/doi.org\/10.1145\/3649476.3658805","relation":{},"subject":[],"published":{"date-parts":[[2024,6,12]]},"assertion":[{"value":"2024-06-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}