{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:02:50Z","timestamp":1755907370244,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T00:00:00Z","timestamp":1718150400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100006374","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2008911,2046186,2051062"],"award-info":[{"award-number":["2008911,2046186,2051062"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,12]]},"DOI":"10.1145\/3649476.3660389","type":"proceedings-article","created":{"date-parts":[[2024,6,10]],"date-time":"2024-06-10T12:29:41Z","timestamp":1718022581000},"page":"663-668","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8347-9368","authenticated-orcid":false,"given":"Siamak","family":"Biglari","sequence":"first","affiliation":[{"name":"University of North Texas, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-6633-893X","authenticated-orcid":false,"given":"Ruixiao","family":"Huang","sequence":"additional","affiliation":[{"name":"University of North Texas, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3683-4077","authenticated-orcid":false,"given":"Hui","family":"Zhao","sequence":"additional","affiliation":[{"name":"Computer Science and Engineering, University of North Texas, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2959-6541","authenticated-orcid":false,"given":"Saraju","family":"Mohanty","sequence":"additional","affiliation":[{"name":"Computer Science and Engineering, University of North Texas, USA"}]}],"member":"320","published-online":{"date-parts":[[2024,6,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477462"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196087"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3392717.3392738"},{"key":"e_1_3_2_1_6_1","unstructured":"Marvell Corporation. 2017. Marvell ARMADA 8040 Quad-Core CA72 Processor with Marvell MoChi and FLC Architecture. (2017). https:\/\/www.marvell.com\/content\/dam\/marvell\/en\/public-collateral\/embedded-processors\/marvell-embedded-processors-armada-7040-product-brief-2017-12.pdf"},{"key":"e_1_3_2_1_7_1","unstructured":"Marvell Corporation. Year not provided. MoChi Architecture. Technical Report. http:\/\/www.marvell.com\/architecture\/mochi\/"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI49217.2020.00062"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ANCS.2019.8901890"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070981"},{"key":"e_1_3_2_1_11_1","unstructured":"L. Gwennap. 2010. Sandy bridge spans generations. Microprocessor Report 9 27 (2010) 10\u201301."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1115\/1.3662552"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.62"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00450-012-0209-1"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS57527.2023.00026"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/90.769767"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3036341"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00091"}],"event":{"name":"GLSVLSI '24: Great Lakes Symposium on VLSI 2024","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Clearwater FL USA","acronym":"GLSVLSI '24"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2024"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3660389","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3649476.3660389","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T02:32:13Z","timestamp":1755829933000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3649476.3660389"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,12]]},"references-count":18,"alternative-id":["10.1145\/3649476.3660389","10.1145\/3649476"],"URL":"https:\/\/doi.org\/10.1145\/3649476.3660389","relation":{},"subject":[],"published":{"date-parts":[[2024,6,12]]},"assertion":[{"value":"2024-06-12","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}