{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T15:40:03Z","timestamp":1755877203912,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":32,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,5,30]],"date-time":"2024-05-30T00:00:00Z","timestamp":1717027200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,5,30]]},"DOI":"10.1145\/3650200.3656604","type":"proceedings-article","created":{"date-parts":[[2024,6,3]],"date-time":"2024-06-03T14:11:54Z","timestamp":1717423914000},"page":"85-97","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["NUCAlloc: Fine-Grained Block Placement in Hashed Last-Level NUCA Caches"],"prefix":"10.1145","author":[{"given":"Raveendra","family":"Soori","sequence":"first","affiliation":[{"name":"Citrix, United States of America"}]},{"given":"Shreyas","family":"Prabhu","sequence":"additional","affiliation":[{"name":"Apple"}]},{"given":"Harpreet Singh","family":"Chawla","sequence":"additional","affiliation":[{"name":"Texas A&M, United States of America"}]},{"given":"Michael","family":"Ferdman","sequence":"additional","affiliation":[{"name":"Stony Brook University, United States of America"}]}],"member":"320","published-online":{"date-parts":[[2024,6,3]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.10"},{"volume-title":"21st International Symposium on High Performance Computer Architecture (HPCA). 538\u2013550","author":"Beckmann N.","key":"e_1_3_2_1_2_1","unstructured":"N. Beckmann, P. Tsai, and D. Sanchez. 2015. Scaling distributed cache hierarchies through computation and data co-scheduling. In 21st International Symposium on High Performance Computer Architecture (HPCA). 538\u2013550."},{"key":"e_1_3_2_1_3_1","unstructured":"Herv\u00e9 Br\u00f6nnimann and Jyrki Katajainen. 2006. Efficiency of various forms of red-black trees. CPH STL Report 2 (2006) 2006."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.39"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.31"},{"key":"e_1_3_2_1_6_1","volume-title":"1st USENIX Conference on Operating Systems Design and Implementation","author":"Dahlin D.","year":"1994","unstructured":"Michael\u00a0D. Dahlin, Randolph\u00a0Y. Wang, Thomas\u00a0E. Anderson, and David\u00a0A. Patterson. 1994. Cooperative Caching: Using Remote Client Memory to Improve File System Performance. In 1st USENIX Conference on Operating Systems Design and Implementation (Monterey, California) (OSDI \u201994). USENIX Association, Berkeley, CA, USA, Article 19."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1966445.1966468"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/11859802_6"},{"key":"e_1_3_2_1_9_1","unstructured":"Jason Evans. 2006. A Scalable Concurrent malloc(3) Implementation for FreeBSD. (2006) 14."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303977"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555779"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088154"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2013.23"},{"key":"e_1_3_2_1_14_1","first-page":"898","article-title":"Seriously, get off my cloud! Cross-VM RSA Key Recovery in a Public Cloud","volume":"2015","author":"Inci Mehmet\u00a0Sinan","year":"2015","unstructured":"Mehmet\u00a0Sinan Inci, Berk Guuml;lmezoglu, Gorka\u00a0Irazoqui Apecechea, Thomas Eisenbarth, and Berk Sunar. 2015. Seriously, get off my cloud! Cross-VM RSA Key Recovery in a Public Cloud. IACR Cryptology ePrint Archive 2015 (2015), 898.","journal-title":"IACR Cryptology ePrint Archive"},{"key":"e_1_3_2_1_15_1","unstructured":"Intel Corporation. 2012. Intel\u00ae Xeon\u00ae Processor E5-2600 Product Family Uncore Performance Monitoring Guide."},{"key":"e_1_3_2_1_16_1","unstructured":"Intel Corporation. 2015. Intel\u00ae Xeon\u00ae Processor E5 and E7 v3 Family Uncore Performance Monitoring Reference Manual."},{"key":"e_1_3_2_1_17_1","unstructured":"Intel Corporation. 2016. Intel\u00ae Xeon\u00ae Processor E5 and E7 v4 Product Families Uncore Performance Monitoring Reference Manual."},{"key":"e_1_3_2_1_18_1","volume-title":"Systematic Reverse Engineering of Cache Slice Selection in Intel Processors. In 2015 Euromicro Conference on Digital System Design(DSD \u201915)","author":"Irazoqui Gorka","year":"2015","unstructured":"Gorka Irazoqui, Thomas Eisenbarth, and Berk Sunar. 2015. Systematic Reverse Engineering of Cache Slice Selection in Intel Processors. In 2015 Euromicro Conference on Digital System Design(DSD \u201915). IEEE Computer Society, Washington, DC, USA, 629\u2013636."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.817393"},{"key":"e_1_3_2_1_20_1","volume-title":"Bank-aware Dynamic Cache Partitioning for Multicore Architectures. In 2009 International Conference on Parallel Processing. 18\u201325","author":"Kaseridis Dimitris","year":"2009","unstructured":"Dimitris Kaseridis, Jeffrey Stuecheli, and Lizy\u00a0K. John. 2009. Bank-aware Dynamic Cache Partitioning for Multicore Architectures. In 2009 International Conference on Parallel Processing. 18\u201325."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2016.7581261"},{"key":"e_1_3_2_1_22_1","volume-title":"Non-uniform Cache Structure for Wire-delay Dominated On-chip Caches. In 10th International Conference on Architectural Support for Programming Languages and Operating Systems","author":"Kim Changkyu","year":"2002","unstructured":"Changkyu Kim, Doug Burger, and Stephen\u00a0W. Keckler. 2002. An Adaptive, Non-uniform Cache Structure for Wire-delay Dominated On-chip Caches. In 10th International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, California) (ASPLOS X). ACM, New York, NY, USA, 211\u2013222."},{"key":"e_1_3_2_1_23_1","unstructured":"Wei-Fen Lin and Steven\u00a0K Reinhardt. 2002. Predicting Last-Touch References under Optimal Replacement. (2002) 17."},{"key":"e_1_3_2_1_24_1","volume-title":"Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters. In 18th International Symposium on Research in Attacks, Intrusions, and Defenses -","volume":"9404","author":"Maurice Cl\u00e9mentine","year":"2015","unstructured":"Cl\u00e9mentine Maurice, Nicolas Scouarnec, Christoph Neumann, Olivier Heen, and Aur\u00e9lien Francillon. 2015. Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters. In 18th International Symposium on Research in Attacks, Intrusions, and Defenses - Volume 9404 (Kyoto, Japan) (RAID 2015). Springer-Verlag New York, Inc., New York, NY, USA, 48\u201365."},{"key":"e_1_3_2_1_25_1","volume-title":"Exploiting Single-Usage for Effective Memory Management. In 12th Asia-Pacific Conference on Advances in Computer Systems Architecture","author":"Piquet Thomas","year":"2007","unstructured":"Thomas Piquet, Olivier Rochecouste, and Andr\u00e9 Seznec. 2007. Exploiting Single-Usage for Effective Memory Management. In 12th Asia-Pacific Conference on Advances in Computer Systems Architecture (Seoul, Korea) (ACSAC \u201907). Springer-Verlag, Berlin, Heidelberg, 90\u2013101."},{"key":"e_1_3_2_1_26_1","volume-title":"Adaptive Insertion Policies for High Performance Caching. In 34th Annual International Symposium on Computer Architecture","author":"Qureshi K.","year":"2007","unstructured":"Moinuddin\u00a0K. Qureshi, Aamer Jaleel, Yale\u00a0N. Patt, Simon\u00a0C. Steely, and Joel Emer. 2007. Adaptive Insertion Policies for High Performance Caching. In 34th Annual International Symposium on Computer Architecture (San Diego, California, USA) (ISCA \u201907). ACM, New York, NY, USA, 381\u2013391."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771796"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.42"},{"key":"e_1_3_2_1_29_1","unstructured":"Thomas Tuttle. 2015. pagemap from the userspace perspective."},{"volume-title":"28th Annual International Symposium on Microarchitecture(MICRO 28)","author":"Tyson G.","key":"e_1_3_2_1_30_1","unstructured":"G. Tyson, M. Farrens, J. Matthews, and A.R. Pleszkun. 1995. A modified approach to data cache management. In 28th Annual International Symposium on Microarchitecture(MICRO 28). 93\u2013103."},{"key":"e_1_3_2_1_31_1","first-page":"905","article-title":"Mapping the Intel Last-Level Cache","volume":"2015","author":"Yarom Yuval","year":"2015","unstructured":"Yuval Yarom, Qian Ge, Fangfei Liu, Ruby\u00a0B. Lee, and Gernot Heiser. 2015. Mapping the Intel Last-Level Cache. IACR Cryptology ePrint Archive 2015 (2015), 905.","journal-title":"IACR Cryptology ePrint Archive"},{"volume-title":"32nd International Symposium on Computer Architecture (ISCA\u201905)","author":"Zhang M.","key":"e_1_3_2_1_32_1","unstructured":"M. Zhang and K. Asanovic. 2005. Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors. In 32nd International Symposium on Computer Architecture (ISCA\u201905). 336\u2013345."}],"event":{"name":"ICS '24: 2024 International Conference on Supercomputing","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Kyoto Japan","acronym":"ICS '24"},"container-title":["Proceedings of the 38th ACM International Conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3650200.3656604","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3650200.3656604","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T15:23:13Z","timestamp":1755876193000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3650200.3656604"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,30]]},"references-count":32,"alternative-id":["10.1145\/3650200.3656604","10.1145\/3650200"],"URL":"https:\/\/doi.org\/10.1145\/3650200.3656604","relation":{},"subject":[],"published":{"date-parts":[[2024,5,30]]},"assertion":[{"value":"2024-06-03","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}