{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T18:48:50Z","timestamp":1764874130554,"version":"3.41.0"},"reference-count":55,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2024,9,17]],"date-time":"2024-09-17T00:00:00Z","timestamp":1726531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc\/4.0\/"}],"funder":[{"name":"RGC General Research Fund","award":["16214123"],"award-info":[{"award-number":["16214123"]}]},{"name":"AI Chip Center for Emerging Smart Systems (ACCESS), Hong Kong SAR"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2024,9,30]]},"abstract":"<jats:p>Multi-die FPGAs are widely adopted for large-scale accelerators, but optimizing high-level synthesis designs on these FPGAs faces two challenges. First, the delay caused by die-crossing nets creates an NP-hard floorplanning problem. Second, traditional directive optimization cannot consider resource constraints on each die or the timing issue incurred by the die-crossings. Furthermore, the high algorithmic complexity and the large scale lead to extended runtime for legalizing the floorplan of HLS designs under different directive configurations.<\/jats:p>\n          <jats:p>To co-optimize the directives and floorplan of HLS designs on multi-die FPGAs, we formulate the co-search based on bin-packing variants and present two iterative optimization flows. The first (FADO 1.0) relies on a pre-built QoR library. It involves a greedy, latency-bottleneck-guided directive search, and an incremental floorplan legalization. Compared with a global floorplanning solution, it takes 693X~4925X shorter search time and achieves 1.16X~8.78X better design performance, measured in workload execution time.<\/jats:p>\n          <jats:p>To remove the time-consuming QoR library generation, the second flow (FADO 2.0) integrates an analytical QoR model and redesigns the directive search to accelerate convergence. Through experiments on mixed dataflow and non-dataflow designs, compared with 1.0, FADO 2.0 further yields a 1.40X better design performance on average after implementation on the Alveo U250 FPGA.<\/jats:p>","DOI":"10.1145\/3653458","type":"journal-article","created":{"date-parts":[[2024,3,20]],"date-time":"2024-03-20T12:09:01Z","timestamp":1710936541000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs"],"prefix":"10.1145","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3007-4890","authenticated-orcid":false,"given":"Linfeng","family":"Du","sequence":"first","affiliation":[{"name":"The Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0390-2320","authenticated-orcid":false,"given":"Tingyuan","family":"Liang","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5878-3683","authenticated-orcid":false,"given":"Xiaofeng","family":"Zhou","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-7986-4886","authenticated-orcid":false,"given":"Jinming","family":"Ge","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-7623-4178","authenticated-orcid":false,"given":"Shangkun","family":"Li","sequence":"additional","affiliation":[{"name":"Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4532-2017","authenticated-orcid":false,"given":"Sharad","family":"Sinha","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Goa, Ponda, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8211-2812","authenticated-orcid":false,"given":"Jieru","family":"Zhao","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4442-592X","authenticated-orcid":false,"given":"Zhiyao","family":"Xie","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7622-6714","authenticated-orcid":false,"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[{"name":"The Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,9,17]]},"reference":[{"key":"e_1_3_2_2_2","first-page":"659","volume-title":"Proceedings of the International Conference on Computational Science","author":"Akbar Md Mostofa","year":"2001","unstructured":"Md Mostofa Akbar, Eric G. Manning, Gholamali C. Shoja, and Shahadat Khan. 2001. Heuristic solutions for the multiple-choice multi-dimension knapsack problem. In Proceedings of the International Conference on Computational Science. Springer, 659\u2013668."},{"issue":"2","key":"e_1_3_2_3_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3470567","article-title":"Elastic-DF: Scaling performance of DNN inference in FPGA clouds through automatic partitioning","volume":"15","author":"Alonso Tobias","year":"2021","unstructured":"Tobias Alonso, Lucian Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, and Kees Vissers. 2021. Elastic-DF: Scaling performance of DNN inference in FPGA clouds through automatic partitioning. ACM Transactions on Reconfigurable Technology and Systems 15, 2 (2021), 1\u201334.","journal-title":"ACM Transactions on Reconfigurable Technology and Systems"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63465-7_226"},{"key":"e_1_3_2_5_2","doi-asserted-by":"crossref","first-page":"279","DOI":"10.1109\/ECTC.2012.6248841","volume-title":"Proceedings of the 2012 IEEE 62nd Electronic Components and Technology Conference","author":"Chaware Raghunandan","year":"2012","unstructured":"Raghunandan Chaware, Kumar Nagarajan, and Suresh Ramalingam. 2012. Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer. In Proceedings of the 2012 IEEE 62nd Electronic Components and Technology Conference. IEEE, 279\u2013283."},{"key":"e_1_3_2_6_2","first-page":"1","volume-title":"Proceedings of the 2018 IEEE\/ACM International Conference on Computer-Aided Design","author":"Cong Jason","year":"2018","unstructured":"Jason Cong and Jie Wang. 2018. PolySA: Polyhedral-based systolic array auto-compilation. In Proceedings of the 2018 IEEE\/ACM International Conference on Computer-Aided Design. IEEE, 1\u20138."},{"key":"e_1_3_2_7_2","doi-asserted-by":"crossref","first-page":"211","DOI":"10.1109\/ICCD.2003.1240897","volume-title":"Proceedings of the 21st International Conference on Computer Design","author":"Deng Yangdong Steven","year":"2003","unstructured":"Yangdong Steven Deng and Wojciech Maly. 2003. Physical design of the \u201d2.5 D\u201d stacked system. In Proceedings of the 21st International Conference on Computer Design. IEEE, 211\u2013217."},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3543622.3573188"},{"issue":"2","key":"e_1_3_2_9_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3570925","article-title":"Graph neural networks for high-level synthesis design space exploration","volume":"28","author":"Ferretti Lorenzo","year":"2022","unstructured":"Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, and Laura Pozzi. 2022. Graph neural networks for high-level synthesis design space exploration. ACM Transactions on Design Automation of Electronic Systems 28, 2 (2022), 1\u201320.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439289"},{"key":"e_1_3_2_11_2","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1145\/2554688.2554776","volume-title":"Proceedings of the 2014 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","author":"Pereira Andre Hahn","year":"2014","unstructured":"Andre Hahn Pereira and Vaughn Betz. 2014. Cad and routing architecture for interposer-based multi-fpga systems. In Proceedings of the 2014 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays. 75\u201384."},{"key":"e_1_3_2_12_2","unstructured":"William L. Hamilton Zhitao Ying and Jure Leskovec. 2017. Inductive representation learning on large graphs. In Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017 December 4-9 2017 Long Beach CA USA 1024\u20131034. Retrieved from https:\/\/proceedings.neurips.cc\/paper\/2017\/hash\/5dd9db5e033da9c6fb5ba83c7a7ebea9-Abstract.html"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541637"},{"key":"e_1_3_2_14_2","unstructured":"Xilinx Inc.2016. UltraRAM: Breakthrough Embedded Memory Integration on UltraScale+ Devices. Retrieved from DOI:https:\/\/docs.xilinx.com\/v\/u\/en-US\/wp477-ultraram"},{"key":"e_1_3_2_15_2","unstructured":"Xilinx Inc.2020. Vitis High-Level Synthesis User Guide. Retrieved from DOI:https:\/\/docs.xilinx.com\/r\/2020.2-English\/ug1399-vitis-hls\/Optimization-Directives"},{"key":"e_1_3_2_16_2","unstructured":"Xilinx Inc.2020. Vitis High-Level Synthesis User Guide. Retrieved from DOI:https:\/\/docs.xilinx.com\/r\/2020.2-English\/ug1399-vitis-hls\/Overview-of-Arbitrary-Precision-Integer-Data-Types"},{"key":"e_1_3_2_17_2","unstructured":"Xilinx Inc.2020. Vitis High-Level Synthesis User Guide. Retrieved from DOI:https:\/\/docs.xilinx.com\/r\/en-US\/ug1399-vitis-hls\/Applying-Optimization-Directives-to-Templates"},{"key":"e_1_3_2_18_2","unstructured":"Xilinx Inc.2020. Vitis High-Level Synthesis User Guide. Retrieved from DOI:https:\/\/docs.xilinx.com\/r\/2020.2-English\/ug1399-vitis-hls\/Automatic-Loop-Pipelining"},{"key":"e_1_3_2_19_2","unstructured":"Xilinx Inc.2021. UltraScale Architecture Memory Resources User Guide. Retrieved from DOI:https:\/\/www.xilinx.com\/support\/documents\/user_guides\/ug573-ultrascale-memory-resources.pdf"},{"key":"e_1_3_2_20_2","unstructured":"Xilinx Inc.2022. Floorplanning With Stacked Silicon Interconnect (SSI) Devices. Retrieved from DOI:https:\/\/docs.xilinx.com\/r\/en-US\/ug906-vivado-design-analysis\/Floorplanning-With-Stacked-Silicon-Interconnect-SSI-Devices"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/3572959"},{"key":"e_1_3_2_22_2","first-page":"416","volume-title":"Proceedings of the Algorithms, Software, Architecture: Information Processing 92: Proceedings of the IFIP 12th World Computer Congress, Madrid, Spain","volume":"1","author":"Karp Richard M.","year":"1992","unstructured":"Richard M. Karp. 1992. On-line algorithms versus off-line algorithms: How much is it worth to know the future?. In Proceedings of the Algorithms, Software, Architecture: Information Processing 92: Proceedings of the IFIP 12th World Computer Congress, Madrid, Spain, Vol. 1. 416."},{"key":"e_1_3_2_23_2","doi-asserted-by":"crossref","first-page":"317","DOI":"10.1007\/978-3-540-24777-7_11","volume-title":"Proceedings of the Knapsack Problems","author":"Kellerer Hans","year":"2004","unstructured":"Hans Kellerer, Ulrich Pferschy, and David Pisinger. 2004. The multiple-choice knapsack problem. In Proceedings of the Knapsack Problems. Springer, 317\u2013347."},{"key":"e_1_3_2_24_2","first-page":"12","volume-title":"Proceedings of the 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines","author":"Khatti Moazin","year":"2023","unstructured":"Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, and Zhenman Fang. 2023. PASTA: Programming and automation support for scalable task-parallel HLS programs on modern multi-die FPGAs. In Proceedings of the 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines. IEEE, 12\u201322."},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.ipl.2010.05.031"},{"key":"e_1_3_2_26_2","first-page":"1","volume-title":"Proceedings of the 2019 IEEE\/ACM International Conference on Computer-Aided Design","author":"Liang Tingyuan","year":"2019","unstructured":"Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, and Wei Zhang. 2019. Hi-clockflow: Multi-clock dataflow automation and throughput optimization in high-level synthesis. In Proceedings of the 2019 IEEE\/ACM International Conference on Computer-Aided Design. IEEE, 1\u20136."},{"key":"e_1_3_2_27_2","unstructured":"Tomofumi Yuki Louis-Noel Pouchet. 2016. PolyBench\/C. Retrieved from DOI:http:\/\/web.cse.ohio-state.edu\/pouchet.2\/software\/polybench\/"},{"key":"e_1_3_2_28_2","doi-asserted-by":"crossref","unstructured":"Edward G Coffman Jr Michael R Garey and David S Johnson. 1984. Approximation algorithms for bin-packing\u2013an updated survey. In Algorithm design for computer system design. Springer 49\u2013106.","DOI":"10.1007\/978-3-7091-4338-4_3"},{"key":"e_1_3_2_29_2","first-page":"93","volume-title":"Proceedings of the 2016 International Great Lakes Symposium on VLSI","author":"Mao Fubing","year":"2016","unstructured":"Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, and Yuchun Ma. 2016. Modular placement for interposer based multi-FPGA systems. In Proceedings of the 2016 International Great Lakes Symposium on VLSI. IEEE, 93\u201398."},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.5555\/98124"},{"key":"e_1_3_2_31_2","doi-asserted-by":"crossref","first-page":"918","DOI":"10.3850\/9783981537079_0350","volume-title":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition","author":"Meng Pingfan","year":"2016","unstructured":"Pingfan Meng, Alric Althoff, Quentin Gautier, and Ryan Kastner. 2016. Adaptive threshold non-pareto elimination: Re-thinking machine learning for system level design space exploration on FPGAs. In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition. IEEE, 918\u2013923."},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2478280"},{"key":"e_1_3_2_33_2","first-page":"248","volume-title":"Proceedings of the Scandinavian Workshop on Algorithm Theory","author":"Patt-Shamir Boaz","year":"2010","unstructured":"Boaz Patt-Shamir and Dror Rawitz. 2010. Vector bin packing with multiple-choice. In Proceedings of the Scandinavian Workshop on Algorithm Theory. Springer, 248\u2013259."},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.5555\/2755753.2755788"},{"issue":"5","key":"e_1_3_2_35_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3126566","article-title":"COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators","volume":"16","author":"Piccolboni Luca","year":"2017","unstructured":"Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P Carloni. 2017. COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators. ACM Transactions on Embedded Computing Systems 16, 5s (2017), 1\u201322.","journal-title":"ACM Transactions on Embedded Computing Systems"},{"key":"e_1_3_2_36_2","first-page":"16","volume-title":"Proceedings of the 2018 28th International Conference on Field Programmable Logic and Applications","author":"Ravishankar Chirag","year":"2018","unstructured":"Chirag Ravishankar, Dinesh Gaitonde, and Trevor Bauer. 2018. Placement strategies for 2.5 D FPGA fabric architectures. In Proceedings of the 2018 28th International Conference on Field Programmable Logic and Applications. IEEE, 16\u2013164."},{"issue":"1","key":"e_1_3_2_37_2","first-page":"1","article-title":"Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency","volume":"1","author":"Saban Kirk","year":"2011","unstructured":"Kirk Saban. 2011. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx, White Paper 1, 1 (2011), 1\u201310.","journal-title":"Xilinx, White Paper"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","unstructured":"Benjamin Carrion Schafer. 2017. Parallel high-level synthesis design space exploration for behavioral IPs of exact latencies. 22 4 Article 65 (may 2017) 20 pages. DOI:10.1145\/3041219","DOI":"10.1145\/3041219"},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2009.5158106"},{"key":"e_1_3_2_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2943570"},{"key":"e_1_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1287\/opre.27.3.503"},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530409"},{"key":"e_1_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.1145\/3494534"},{"key":"e_1_3_2_44_2","unstructured":"Petar Velickovic Guillem Cucurull Arantxa Casanova Adriana Romero Pietro Li\u00f2 and Yoshua Bengio. 2017. Graph attention networks. CoRR abs\/1710.10903 (2017). Retrieved from http:\/\/arxiv.org\/abs\/1710.10903"},{"key":"e_1_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439292"},{"key":"e_1_3_2_46_2","first-page":"145","volume-title":"Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition","author":"Wang Zi","year":"2020","unstructured":"Zi Wang, Jianqi Chen, and Benjamin Carrion Schafer. 2020. Efficient and robust high-level synthesis design space exploration through offline micro-kernels pre-characterization. In Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition. IEEE, 145\u2013150."},{"key":"e_1_3_2_47_2","first-page":"39","volume-title":"Proceedings of the 2021 on Great Lakes Symposium on VLSI","author":"Wu Nan","year":"2021","unstructured":"Nan Wu, Yuan Xie, and Cong Hao. 2021. Ironman: Gnn-assisted design space exploration in high-level synthesis via reinforcement learning. In Proceedings of the 2021 on Great Lakes Symposium on VLSI. 39\u201344."},{"key":"e_1_3_2_48_2","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530408"},{"key":"e_1_3_2_49_2","unstructured":"Xilinx. 2022. Vitis Accelerated Libraries. Retrieved from DOI:https:\/\/github.com\/Xilinx\/Vitis_Libraries\/"},{"key":"e_1_3_2_50_2","unstructured":"Xilinx. 2023. Vitis Data Center Acceleration Examples: Stream Chain Matrix Multiplication (C). Retrieved from DOI:https:\/\/github.com\/Xilinx\/Vitis_Accel_Examples\/blob\/main\/host_xrt\/kernel_chain\/README.rst"},{"key":"e_1_3_2_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.56"},{"key":"e_1_3_2_52_2","first-page":"741","volume-title":"Proceedings of the 2022 IEEE International Symposium on High-Performance Computer Architecture","author":"Ye Hanchen","year":"2022","unstructured":"Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, and Deming Chen. 2022. Scalehls: A new scalable high-level synthesis framework on multi-level intermediate representation. In Proceedings of the 2022 IEEE International Symposium on High-Performance Computer Architecture. IEEE, 741\u2013755."},{"key":"e_1_3_2_53_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465827"},{"key":"e_1_3_2_54_2","first-page":"91","volume-title":"Proceedings of the 2018 International Conference on High Performance Computing & Simulation","author":"Zacharopoulos Georgios","year":"2018","unstructured":"Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, and Laura Pozzi. 2018. Machine learning approach for loop unrolling factor prediction in high level synthesis. In Proceedings of the 2018 International Conference on High Performance Computing & Simulation. IEEE, 91\u201397."},{"key":"e_1_3_2_55_2","first-page":"430","volume-title":"Proceedings of the 2017 IEEE\/ACM International Conference on Computer-Aided Design","author":"Zhao Jieru","year":"2017","unstructured":"Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, and Bingsheng He. 2017. COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. In Proceedings of the 2017 IEEE\/ACM International Conference on Computer-Aided Design. IEEE, 430\u2013437."},{"key":"e_1_3_2_56_2","doi-asserted-by":"publisher","unstructured":"Yuan Zhou Udit Gupta Steve Dai Ritchie Zhao Nitish Kumar Srivastava Hanchen Jin Joseph Featherston Yi-Hsiang Lai Gai Liu Gustavo Angarita Velasquez Wenping Wang and Zhiru Zhang. 2018. Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs. In Proceedings of the 2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays FPGA 2018 Monterey CA USA February 25-27 2018 ACM 269\u2013278. DOI:10.1145\/3174243.3174255","DOI":"10.1145\/3174243.3174255"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3653458","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3653458","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T23:44:26Z","timestamp":1750290266000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3653458"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,17]]},"references-count":55,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2024,9,30]]}},"alternative-id":["10.1145\/3653458"],"URL":"https:\/\/doi.org\/10.1145\/3653458","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2024,9,17]]},"assertion":[{"value":"2023-09-10","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-03-10","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-09-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}