{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:07:55Z","timestamp":1755907675435,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,1,19]],"date-time":"2024-01-19T00:00:00Z","timestamp":1705622400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Hunan Provincial Natural Science Foundation of China","award":["2023JJ60217"],"award-info":[{"award-number":["2023JJ60217"]}]},{"name":"Special Funding Projects for Promoting High-Quality Development of Marine and Fishery Industry of Fujian Province","award":["FJHYF-ZH-2023-06"],"award-info":[{"award-number":["FJHYF-ZH-2023-06"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,1,19]]},"DOI":"10.1145\/3653781.3653827","type":"proceedings-article","created":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T12:22:26Z","timestamp":1717244546000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Research on Key Technologies for Intelligent Detection of High-Speed Railway Pantograph System Status Based on Deep learning"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-9860-4968","authenticated-orcid":false,"given":"Rong","family":"Wang","sequence":"first","affiliation":[{"name":"Hunan Automotive Engineering Vocational College, China and \rThe College of Electrical Engineering and Automation, Fuzhou University, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-4304-6277","authenticated-orcid":false,"given":"Shenglan","family":"Chen","sequence":"additional","affiliation":[{"name":"The College of Automation, Central South University, China and \rCRRC Times Co., LTD, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7884-6714","authenticated-orcid":false,"given":"Jun","family":"Wang","sequence":"additional","affiliation":[{"name":"The College of Electrical Engineering and Automation, Fuzhou University, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-3487-6042","authenticated-orcid":false,"given":"Wenchen","family":"Chen","sequence":"additional","affiliation":[{"name":"The College of Electrical Engineering and Automation, Fuzhou University, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-5604-8513","authenticated-orcid":false,"given":"Hai","family":"Pei","sequence":"additional","affiliation":[{"name":"The College of Electrical Engineering and Automation, Fuzhou University, China"}]}],"member":"320","published-online":{"date-parts":[[2024,6]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2023.3330798"},{"key":"e_1_3_2_1_2_1","volume-title":"UIC Standard IRS70014","author":"Application-Fixed Railway","year":"2016","unstructured":"Railway Application-Fixed Insta llations Maintenance Guidelines for OCL , UIC Standard IRS70014, 2016."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2019.2897583"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2017.2720721"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2014.2307955"},{"key":"e_1_3_2_1_6_1","volume-title":"FPGA Implementation of MobileNetV2 CNN Model Using Semi-Streaming Architecture for Low Power Inference Applications[C].2020 IEEE Intl Conf on Parallel & Distributed Processing with Applications","author":"Shaydyuk N. K.","year":"2020","unstructured":"N. K. Shaydyuk and E. B. John.FPGA Implementation of MobileNetV2 CNN Model Using Semi-Streaming Architecture for Low Power Inference Applications[C].2020 IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2020:160-167."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"J. Knapheide B. Stabernack High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution[C]. 2020:277-283.","DOI":"10.1109\/FPL50879.2020.00053"},{"key":"e_1_3_2_1_8_1","first-page":"2692","article-title":"Optimizing Hardware Accelerated General Matrix-Matrix Multiplication for CNNs on FPGAs[J].","volume":"2020","author":"Ahmad A.","unstructured":"A. Ahmad and M. A. Pasha.Optimizing Hardware Accelerated General Matrix-Matrix Multiplication for CNNs on FPGAs[J].IEEE Transactions on Circuits and Systems II: Express Briefs,2020,67[11]:2692-2696.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"}],"event":{"name":"CVDL 2024: The International Conference on Computer Vision and Deep Learning","acronym":"CVDL 2024","location":"Changsha China"},"container-title":["Proceedings of the International Conference on Computer Vision and Deep Learning"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3653781.3653827","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3653781.3653827","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T15:26:41Z","timestamp":1755876401000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3653781.3653827"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1,19]]},"references-count":8,"alternative-id":["10.1145\/3653781.3653827","10.1145\/3653804"],"URL":"https:\/\/doi.org\/10.1145\/3653781.3653827","relation":{},"subject":[],"published":{"date-parts":[[2024,1,19]]},"assertion":[{"value":"2024-06-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}