{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:08:42Z","timestamp":1755907722679,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":61,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,13]],"date-time":"2024-10-13T00:00:00Z","timestamp":1728777600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100006374","name":"National Science Foundation","doi-asserted-by":"publisher","award":["SHF-2217395, CCF-2114319, CNS-1909099"],"award-info":[{"award-number":["SHF-2217395, CCF-2114319, CNS-1909099"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,14]]},"DOI":"10.1145\/3656019.3676948","type":"proceedings-article","created":{"date-parts":[[2024,10,11]],"date-time":"2024-10-11T10:34:08Z","timestamp":1728642848000},"page":"219-232","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Parallel Loop Locality Analysis for Symbolic Thread Counts"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0715-7313","authenticated-orcid":false,"given":"Fangzhou","family":"Liu","sequence":"first","affiliation":[{"name":"University of Rochester, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-6718-7787","authenticated-orcid":false,"given":"Yifan","family":"Zhu","sequence":"additional","affiliation":[{"name":"University of Rochester, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-4333-7858","authenticated-orcid":false,"given":"Shaotong","family":"Sun","sequence":"additional","affiliation":[{"name":"University of Rochester, United States"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4968-6659","authenticated-orcid":false,"given":"Chen","family":"Ding","sequence":"additional","affiliation":[{"name":"University of Rochester, United States"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4429-0623","authenticated-orcid":false,"given":"Wesley","family":"Smith","sequence":"additional","affiliation":[{"name":"University of Rochester, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3497-3500","authenticated-orcid":false,"given":"Kaave Seyed","family":"Hosseini","sequence":"additional","affiliation":[{"name":"University of Rochester, USA"}]}],"member":"320","published-online":{"date-parts":[[2024,10,13]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"30th ACM SIGPLAN International Conference on Compiler Construction, Virtual Event, Republic of Korea","author":"Carollo-Fern\u00e1ndez Pedro","year":"2021","unstructured":"Miguel\u00a0\u00c1. Abella-Gonz\u00e1lez, Pedro Carollo-Fern\u00e1ndez, Louis-No\u00ebl Pouchet, Fabrice Rastello, and Gabriel Rodr\u00edguez. 2021. PolyBench\/Python: benchmarking Python environments with polyhedral optimizations. In CC \u201921: 30th ACM SIGPLAN International Conference on Compiler Construction, Virtual Event, Republic of Korea, March 2-3, 2021. 59\u201370."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2688500.2688512"},{"volume-title":"Optimizing Compilers for Modern Architectures: A Dependence-based Approach","author":"Allen Randy","key":"e_1_3_2_1_3_1","unstructured":"Randy Allen and Ken Kennedy. 2001. Optimizing Compilers for Modern Architectures: A Dependence-based Approach. Morgan Kaufmann Publishers."},{"key":"e_1_3_2_1_4_1","volume-title":"Beyond Iteration Vectors: Instancewise Relational Abstract Domains. In 13th International Symposium on Static Analysis (SAS)(Lecture Notes in Computer Science, Vol.\u00a04134)","author":"Amiranoff Pierre","year":"2006","unstructured":"Pierre Amiranoff, Albert Cohen, and Paul Feautrier. 2006. Beyond Iteration Vectors: Instancewise Relational Abstract Domains. In 13th International Symposium on Static Analysis (SAS)(Lecture Notes in Computer Science, Vol.\u00a04134), Kwangkeun Yi (Ed.). Springer, 161\u2013180."},{"key":"e_1_3_2_1_5_1","volume-title":"2020 International Conference on Supercomputing","author":"Arafa Yehia","year":"2020","unstructured":"Yehia Arafa, Abdel-Hameed\u00a0A. Badawy, Gopinath Chennupati, Atanu Barai, Nandakishore Santhi, and Stephan\u00a0J. Eidenbenz. 2020. Fast, accurate, and scalable memory modeling of GPGPUs using reuse profiles. In ICS \u201920: 2020 International Conference on Supercomputing, Barcelona Spain, June, 2020. 31:1\u201331:12."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2019.8661197"},{"key":"e_1_3_2_1_7_1","volume-title":"Proceedings of the ACM on Programming Languages 2, POPL","author":"Bao Wenlei","year":"2018","unstructured":"Wenlei Bao, Sriram Krishnamoorthy, Louis-No\u00ebl Pouchet, and P. Sadayappan. 2018. Analytical modeling of cache behavior for affine programs. Proceedings of the ACM on Programming Languages 2, POPL (2018), 32:1\u201332:26."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3422575.3422806"},{"volume-title":"Proceedings of High Performance Computing and Communications","author":"Beyls Kristof","key":"e_1_3_2_1_9_1","unstructured":"Kristof Beyls and Erik\u00a0H. D\u2019Hollander. 2006. Discovery of locality-improving refactoring by reuse path analysis. In Proceedings of High Performance Computing and Communications. Springer. Lecture Notes in Computer Science, Vol.\u00a04208. 220\u2013229."},{"volume-title":"Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation. 101\u2013113","author":"Bondhugula Uday","key":"e_1_3_2_1_10_1","unstructured":"Uday Bondhugula, Albert Hartono, J. Ramanujam, and P. Sadayappan. 2008. A practical automatic polyhedral parallelizer and locality optimizer. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation. 101\u2013113."},{"key":"e_1_3_2_1_11_1","volume-title":"A Survey of Cache Simulators. ACM Comput. Surv. 53, 1","author":"Brais Hadi","year":"2021","unstructured":"Hadi Brais, Rajshekar Kalayappan, and Preeti\u00a0Ranjan Panda. 2021. A Survey of Cache Simulators. ACM Comput. Surv. 53, 1 (2021), 19:1\u201319:32."},{"key":"e_1_3_2_1_12_1","volume-title":"Bruening and Saman Amarasinghe","author":"L.","year":"2004","unstructured":"Derek\u00a0L. Bruening and Saman Amarasinghe. 2004. Efficient, Transparent, and Comprehensive Runtime Code Manipulation. Ph.\u00a0D. Dissertation. USA. AAI0807735."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1177\/109434200001400404"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"e_1_3_2_1_15_1","volume-title":"Efficient Miss Ratio Curve Computation for Heterogeneous Content Popularity. In 2020 USENIX Annual Technical Conference (USENIX ATC 20)","author":"Carra Damiano","year":"2020","unstructured":"Damiano Carra and Giovanni Neglia. 2020. Efficient Miss Ratio Curve Computation for Heterogeneous Content Popularity. In 2020 USENIX Annual Technical Conference (USENIX ATC 20). 741\u2013751."},{"key":"e_1_3_2_1_16_1","volume-title":"Proceedings of the International Conference on Supercomputing. 150\u2013159","author":"Cascaval Calin","year":"2003","unstructured":"Calin Cascaval and David\u00a0A. Padua. 2003. Estimating cache misses and locality using stack distances. In Proceedings of the International Conference on Supercomputing. 150\u2013159."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3459898.3463908"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192402"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/363095.363141"},{"key":"e_1_3_2_1_20_1","unstructured":"Chen Ding and Trishul Chilimbi. 2009. A Composable Model for Analyzing Locality of Multi-threaded Programs. Technical Report MSR-TR-2009-107. Microsoft Research."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944885"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452069"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2676726.2677010"},{"key":"e_1_3_2_1_24_1","volume-title":"Proceedings of the International Conference on Parallel Architecture and Compilation Techniques. 27\u201337","author":"Fang Changpeng","year":"2005","unstructured":"Changpeng Fang, Steve Carr, Soner \u00d6nder, and Zhenlin Wang. 2005. Instruction Based Memory Distance Analysis and its Application. In Proceedings of the International Conference on Parallel Architecture and Compilation Techniques. 27\u201337."},{"key":"e_1_3_2_1_25_1","volume-title":"Cache-Oblivious Algorithms. In Proceedings of the Symposium on Foundations of Computer Science. 285\u2013298","author":"Frigo Matteo","year":"1999","unstructured":"Matteo Frigo, Charles\u00a0E. Leiserson, Harald Prokop, and Sridhar Ramachandran. 1999. Cache-Oblivious Algorithms. In Proceedings of the Symposium on Foundations of Computer Science. 285\u2013298."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3109482"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/325478.325479"},{"volume-title":"GNU scientific library reference manual","author":"Gough Brian","key":"e_1_3_2_1_28_1","unstructured":"Brian Gough. 2009. GNU scientific library reference manual. Network Theory Ltd."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314606"},{"key":"e_1_3_2_1_30_1","volume-title":"Proceedings of the ACM Conference on Theory of Computing","author":"Hong Jia-Wei","year":"1981","unstructured":"Jia-Wei Hong and H.\u00a0T. Kung. 1981. I\/O complexity: The red-blue pebble game. In Proceedings of the ACM Conference on Theory of Computing. Milwaukee, WI, 326\u2013333."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3185751"},{"volume-title":"Proceedings of the International Conference on Measurement and Modeling of Computer Systems. Marina Del Rey, California.","author":"Jiang S.","key":"e_1_3_2_1_32_1","unstructured":"S. Jiang and X. Zhang. 2002. LIRS: an efficient low inter-reference recency set replacement to improve buffer cache performance. In Proceedings of the International Conference on Measurement and Modeling of Computer Systems. Marina Del Rey, California."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11970-5_15"},{"key":"e_1_3_2_1_34_1","unstructured":"Karl Rupp. 2018. 42 Years of Microprocessor Trend Data. https:\/\/www.karlrupp.net\/2018\/02\/42-years-of-microprocessor-trend-data\/"},{"volume-title":"Markov Chains and Mixing Times","author":"Levin David","key":"e_1_3_2_1_35_1","unstructured":"David Levin, Yuval Peres, and Elizabeth Wilmer. 2017. Markov Chains and Mixing Times: Second Edition. American Mathematical Society."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3046678"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","unstructured":"Fangzhou Liu Yifan Zhu and Shaotong Sun. 2024. Parallel Loop Locality Analysis for Symbolic Thread Counts (Artifacts). https:\/\/doi.org\/10.5281\/zenodo.12738741","DOI":"10.5281\/zenodo.12738741"},{"key":"e_1_3_2_1_38_1","unstructured":"Louis-Noel Pouchet and Tomofumi Yuki. 2018. PolyBench\/C 4.2. http:\/\/https:\/\/sourceforge.net\/projects\/polybench\/files\/"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240302.3240419"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3018743.3018759"},{"volume-title":"Proceedings of the International Conference on Measurement and Modeling of Computer Systems. 2\u201313","author":"Marin G.","key":"e_1_3_2_1_42_1","unstructured":"G. Marin and J. Mellor-Crummey. 2004. Cross architecture performance predictions for scientific applications using parameterized models. In Proceedings of the International Conference on Measurement and Modeling of Computer Systems. 2\u201313."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694364"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250746"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385989"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2896633"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3484199"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854286"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/3293883.3295735"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314592"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400713"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00056"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/3447818.3460379"},{"key":"e_1_3_2_1_54_1","volume-title":"Proceedings of the Symposium on Operating Systems Design and Implementation. USENIX Association, 335\u2013349","author":"Wires Jake","year":"2014","unstructured":"Jake Wires, Stephen Ingram, Zachary Drudi, Nicholas\u00a0JA Harvey, Andrew Warfield, and Coho Data. 2014. Characterizing storage workloads with counter stacks. In Proceedings of the Symposium on Operating Systems Design and Implementation. USENIX Association, 335\u2013349."},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/2427631.2427632"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.58"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941567"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451153"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/3134437"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3341109"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/1552309.1552310"}],"event":{"name":"PACT '24: International Conference on Parallel Architectures and Compilation Techniques","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Long Beach CA USA","acronym":"PACT '24"},"container-title":["Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3656019.3676948","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3656019.3676948","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T19:56:36Z","timestamp":1755892596000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3656019.3676948"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,13]]},"references-count":61,"alternative-id":["10.1145\/3656019.3676948","10.1145\/3656019"],"URL":"https:\/\/doi.org\/10.1145\/3656019.3676948","relation":{},"subject":[],"published":{"date-parts":[[2024,10,13]]},"assertion":[{"value":"2024-10-13","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}