{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,9]],"date-time":"2026-06-09T08:42:23Z","timestamp":1780994543375,"version":"3.54.1"},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"PLDI","license":[{"start":{"date-parts":[[2024,6,20]],"date-time":"2024-06-20T00:00:00Z","timestamp":1718841600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Program. Lang."],"published-print":{"date-parts":[[2024,6,20]]},"abstract":"<jats:p>Modular design is critical in reducing hardware designer\u2019s cognitive load and development cost. However, it is challenging to modularize high-performance pipelined circuits with structural, data, and control hazards because their resolution\u2014stalling, and bypassing, and discard-and-restarting\u2014introduce cross-stage dependencies. The dependencies could potentially mandate monolithic control logic and create combinational loops, hindering modular design. An effective method to modularize pipelined circuits is valid-ready interfaces, but they apply to a relatively simple form of pipelined circuits only with structural hazards.<\/jats:p>\n          <jats:p>\n            We propose\n            <jats:italic toggle=\"yes\">hazard interfaces,<\/jats:italic>\n            a generalization of valid-ready interfaces that can modularize pipelined circuits not only with structural but also with data and control hazards. The key idea is enveloping the cross-stage dependencies within interfaces. We also design combinators for hazard interfaces in the style of map-reduce that facilitate decomposition of control logic. We implement a compiler (to synthesizable Verilog) for a prototype language supporting hazard interfaces and combinators, and design a sound and efficient type checker that proves the absence of combinational loops. With case studies on 5-stage RISC-V CPU core and 100 Gbps Ethernet NIC, we demonstrate that hazard interfaces indeed facilitate modular design while incurring no noticeable cost in performance, power, and area over reference designs in Chisel and Verilog.\n          <\/jats:p>\n          <jats:p>\n            CCS Concepts: \u2022\n            <jats:bold>Hardware \u2192 Hardware description languages and compilation<\/jats:bold>\n            ; \u2022\n            <jats:bold>Software and its engineering \u2192 Functional languages<\/jats:bold>\n            .\n          <\/jats:p>","DOI":"10.1145\/3656378","type":"journal-article","created":{"date-parts":[[2024,6,20]],"date-time":"2024-06-20T16:27:20Z","timestamp":1718900840000},"page":"28-51","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Modular Hardware Design of Pipelined Circuits with Hazards"],"prefix":"10.1145","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8627-822X","authenticated-orcid":false,"given":"Minseong","family":"Jang","sequence":"first","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-4462-3895","authenticated-orcid":false,"given":"Jungin","family":"Rhee","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-6964-0694","authenticated-orcid":false,"given":"Woojin","family":"Lee","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-7145-1610","authenticated-orcid":false,"given":"Shuangshuang","family":"Zhao","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2115-0871","authenticated-orcid":false,"given":"Jeehoon","family":"Kang","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,6,20]]},"reference":[{"key":"e_1_3_1_2_1","unstructured":"Advanced Micro Devices Inc. 2022. AXI Register Slice. https:\/\/www.xilinx.com\/products\/intellectual-property\/axi-register-slice.html"},{"key":"e_1_3_1_3_1","doi-asserted-by":"crossref","unstructured":"T Ajayi D Blaauw TB Chan CK Cheng VA Chhabria DK Choo M Coltella S Dobre R Dreslinski M Foga\u00e7a et al. 2019 OpenROAD: Toward a Self-Driving Open-Source Digital Layout Implementation Tool Chain. Proc. GOMACTECH (2019) $1105-1110$","DOI":"10.1145\/3316781.3326334"},{"key":"e_1_3_1_4_1","unstructured":"Jens Axboe. 2017. fio - Flexible I\/O tester. https:\/\/fio.readthedocs.io\/en\/latest\/fio_doc.html"},{"key":"e_1_3_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_1_6_1","unstructured":"Berkeley Architecture Research. 2021. Sodor Core. https:\/\/github.com\/ucb-bar\/riscv-sodor\/tree\/sodor-old"},{"key":"e_1_3_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/289423.289440"},{"key":"e_1_3_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385965"},{"key":"e_1_3_1_9_1","doi-asserted-by":"crossref","unstructured":"L.P. Carloni K.L. McMillan and A.L. Sangiovanni-Vincentelli. 2001. Theory of latency-insensitive design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 9 (2001) 1059-1076. https:\/\/doi.org\/10.1109\/43.945302","DOI":"10.1109\/43.945302"},{"key":"e_1_3_1_10_1","volume-title":"Ph. D. Dissertation EECS Department","author":"Celio Christopher","year":"2018","unstructured":"Christopher Celio. 2018. A Highly Productive Implementation of an Out-of-Order Processor Generator. Ph. D. Dissertation EECS Department, University of California, Berkeley. http:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2018\/EECS-2018-151.html"},{"key":"e_1_3_1_11_1","doi-asserted-by":"crossref","unstructured":"Joonwon Choi Muralidaran Vijayaraghavan Benjamin Sherman Adam Chlipala and Arvind. 2017. Kami: a platform for high-level parametric hardware specification and its modular verification. Proc. ACM Program. Lang. 1 ICFP Article 24 (aug 2017) 30 pages. https:\/\/doi.org\/10.1145\/3110268","DOI":"10.1145\/3110268"},{"key":"e_1_3_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3453483.3454037"},{"key":"e_1_3_1_13_1","doi-asserted-by":"crossref","unstructured":"John Clow Georgios Tzimpragos Deeksha Dangwal Sammy Guo Joseph McMahan and Timothy Sherwood. 2017. A pythonic approach for rapid hardware prototyping and instrumentation. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL). 1-7. https:\/\/doi.org\/10.23919\/FPL.2017.8056860","DOI":"10.23919\/FPL.2017.8056860"},{"key":"e_1_3_1_14_1","doi-asserted-by":"crossref","unstructured":"Deeksha Dangwal Georgios Tzimpragos and Timothy Sherwood. 2020. Agile Hardware Development and Instrumentation With PyRTL. IEEE Micro 40 4 (2020) 76-84. https:\/\/doi.org\/10.1109\/MM.2020.2997704","DOI":"10.1109\/MM.2020.2997704"},{"key":"e_1_3_1_15_1","doi-asserted-by":"crossref","unstructured":"Jeffrey Dean and Sanjay Ghemawat. 2008. MapReduce: Simplified Data Processing on Large Clusters. Commun. ACM 51 1 (jan 2008) 107-113. https:\/\/doi.org\/10.1145\/1327452.1327492","DOI":"10.1145\/1327452.1327492"},{"key":"e_1_3_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385983"},{"key":"e_1_3_1_17_1","unstructured":"Embedded Microprocessor Benchmark Consortium. 2023 EEMBC https:\/\/www.eembc.org\/"},{"key":"e_1_3_1_18_1","doi-asserted-by":"crossref","unstructured":"Alex Forencich Alex C. Snoeren George Porter and George Papen. 2020. Corundum: An Open-Source 100-Gbps Nic. In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 38-46. https:\/\/doi.org\/10.1109\/FCCM48280.2020.00015","DOI":"10.1109\/FCCM48280.2020.00015"},{"key":"e_1_3_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3575693.3575701"},{"key":"e_1_3_1_20_1","doi-asserted-by":"crossref","unstructured":"Steven F. Hoover. 2017. Timing-Abstract Circuit Design in Transaction-Level Verilog. In 2017 IEEE International Conference on Computer Design (ICCD). 525-532. https:\/\/doi.org\/10.1109\/ICCD.2017.91","DOI":"10.1109\/ICCD.2017.91"},{"key":"e_1_3_1_21_1","doi-asserted-by":"crossref","unstructured":"Minseong Jang Jungin Rhee Woojin Lee Shuangshuang Zhao and Jeehoon Kang. 2024. Modular Hardware Design of Pipelined Circuits with Hazards (artifact and appendix). https:\/\/doi.org\/10.5281\/zenodo.10906305 Project webpage: https:\/\/cp.kaist.ac.kr\/fpga.","DOI":"10.1145\/3656378"},{"key":"e_1_3_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3315454.3329957"},{"key":"e_1_3_1_23_1","doi-asserted-by":"crossref","unstructured":"Yanbing Li and M. Leeser. 1995. HML: an innovative hardware description language and its translation to VHDL. In Proceedings of ASP-DAC\u201995\/CHDL\u201995\/VLSI\u201995 with EDA Technofair. 691-696. https:\/\/doi.org\/10.1109\/ASPDAC.1995.486388","DOI":"10.1109\/ASPDAC.1995.486388"},{"key":"e_1_3_1_24_1","doi-asserted-by":"crossref","unstructured":"R. Nikhil. 2004. Bluespec System Verilog: efficient correct RTL from high level specifications. In Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design 2004. MEMOCODE \u201904. 69-70. https:\/\/doi.org\/10.1109\/MEMCOD.2004.1459818","DOI":"10.1109\/MEMCOD.2004.1459818"},{"key":"e_1_3_1_25_1","doi-asserted-by":"crossref","unstructured":"J. O\u2019Donnell. 2002. Overview of hydra: a concurrent language for synchronous digital circuit design. In Proceedings 16th International Parallel and Distributed Processing Symposium. 9 pp-. https:\/\/doi.org\/10.1109\/IPDPS.2002.1016653","DOI":"10.1109\/IPDPS.2002.1016653"},{"key":"e_1_3_1_26_1","doi-asserted-by":"crossref","unstructured":"Brandon Reagen Robert Adolf Yakun Sophia Shao Gu-Yeon Wei and David Brooks. 2014. MachSuite: Benchmarks for accelerator design and customized architectures. In 2014 IEEE International Symposium on Workload Characterization (IISWC). 110-119. https:\/\/doi.org\/10.1109\/IISWC.2014.6983050","DOI":"10.1109\/IISWC.2014.6983050"},{"key":"e_1_3_1_27_1","first-page":"104","volume-title":"ACM Symposium on LISP and Functional Programming (Austin, Texas, USA) (LFP \u201984)","author":"Sheeran Mary","year":"1984","unstructured":"Mary Sheeran. 1984. muFP, a language for VLSI design. In Proceedings of the 1984 ACM Symposium on LISP and Functional Programming (Austin, Texas, USA) (LFP \u201984). Association for Computing Machinery, New York, NY, USA, 104-112. https:\/\/doi.org\/10.1145\/800055.802026"},{"key":"e_1_3_1_28_1","unstructured":"Satnam Singh. 2021. Hardware Design and Verification with Cava. https:\/\/talks.ee.ic.ac.uk\/talk\/index\/1224"},{"key":"e_1_3_1_29_1","unstructured":"Frans Skarman and Oscar Gustafsson. 2023. Spade: An Expression-Based HDL With Pipelines. arXiv:2304.03079 [cs.AR]"},{"key":"e_1_3_1_30_1","unstructured":"Wilson Snyder. 2024. Verilator. https:\/\/www.veripool.org\/verilator\/"},{"key":"e_1_3_1_31_1","doi-asserted-by":"crossref","unstructured":"Michael Bedford Taylor. 2018. Basejump STL: systemverilog needs a standard template library for hardware design. In Proceedings of the 55th Annual Design Automation Conference (San Francisco California) (DAC \u201918). Association for Computing Machinery New York NY USA Article 73 6 pages. https:\/\/doi.org\/10.1145\/3195970.3199848","DOI":"10.1145\/3195970.3199848"},{"key":"e_1_3_1_32_1","doi-asserted-by":"publisher","DOI":"10.3990\/1.9789036538879"},{"key":"e_1_3_1_33_1","unstructured":"Wikipedia contributors. 2024. Finite impulse response - Wikipedia The Free Encyclopedia. https:\/\/en.wikipedia.org\/w\/index.php?title=Finite_impulse_response%26oldid=1172063361 [Online; accessed 6-April-2024]."},{"key":"e_1_3_1_34_1","unstructured":"Claire Wolf. 2024. Yosys Open SYnthesis Suite. https:\/\/yosyshq.net\/yosys\/."},{"key":"e_1_3_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3519939.3523455"},{"key":"e_1_3_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"}],"container-title":["Proceedings of the ACM on Programming Languages"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3656378","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3656378","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T20:42:30Z","timestamp":1751661750000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3656378"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,20]]},"references-count":35,"journal-issue":{"issue":"PLDI","published-print":{"date-parts":[[2024,6,20]]}},"alternative-id":["10.1145\/3656378"],"URL":"https:\/\/doi.org\/10.1145\/3656378","relation":{},"ISSN":["2475-1421"],"issn-type":[{"value":"2475-1421","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,6,20]]},"assertion":[{"value":"2024-06-20","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}