{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:05:02Z","timestamp":1750309502056,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T00:00:00Z","timestamp":1737331200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,1,20]]},"DOI":"10.1145\/3658617.3697636","type":"proceedings-article","created":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T14:32:21Z","timestamp":1741098741000},"page":"548-553","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-4953-6680","authenticated-orcid":false,"given":"Haojia","family":"Hui","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Tsinghua Univ., Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1190-7524","authenticated-orcid":false,"given":"Jiangyuan","family":"Gu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua Univ., Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-6552-1587","authenticated-orcid":false,"given":"Xunbo","family":"Hu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua Univ., Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5117-7920","authenticated-orcid":false,"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua Univ., Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2309-572X","authenticated-orcid":false,"given":"Shouyi","family":"Yin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua Univ., Beijing, China"},{"name":"Integrated Circuit Research Platform, International lnnovation Center of Tsinghua Univ., Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,3,4]]},"reference":[{"unstructured":"Krste Asanovi\u0107 Rimas Avizienis et al. 2016. The Rocket Chip Generator. Technical Report. EECS Department University of California Berkeley.","key":"e_1_3_2_1_1_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1145\/2228360.2228584"},{"doi-asserted-by":"crossref","unstructured":"Jinyi Deng Linyun Zhang et al. 2022. Mixed-granularity parallel coarse-grained reconfigurable architecture. In DAC. 343--348.","key":"e_1_3_2_1_3_1","DOI":"10.1145\/3489517.3530454"},{"key":"e_1_3_2_1_4_1","volume-title":"Riptide: A programmable, energy-minimal dataflow compiler and architecture. In MICRO.","author":"Gobieski Graham","year":"2022","unstructured":"Graham Gobieski, Souradip Ghosh, Marijn Heule, Todd Mowry, Tony Nowatzki, Nathan Beckmann, and Brandon Lucia. 2022. Riptide: A programmable, energy-minimal dataflow compiler and architecture. In MICRO."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1145\/3282307"},{"unstructured":"junxiaosong. 2017. AlphaZero-Gomoku. In https:\/\/github.com\/junxiaosong\/AlphaZero-Gomoku.","key":"e_1_3_2_1_6_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1145\/3489517.3530453"},{"doi-asserted-by":"crossref","unstructured":"Derek Lockhart Gary Zibrat and Christopher Batten. 2014. PyMTL: A unified framework for vertically integrated computer architecture research. In MICRO.","key":"e_1_3_2_1_8_1","DOI":"10.1109\/MICRO.2014.50"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1145\/3079856.3080255"},{"unstructured":"C. Papon. 2014. https:\/\/github.com\/SpinalHDL\/VexRiscv. In VexRiscv.","key":"e_1_3_2_1_10_1"},{"unstructured":"C. Papon. 2014. https:\/\/spinalhdl.github.io\/SpinalDoc-RTD\/v1.3.1\/index.html. In SpinalHDL Documentation.","key":"e_1_3_2_1_11_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1109\/ACCESS.2020.3012084"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.1145\/3140659.3080256"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1109\/JPROC.2014.2386883"},{"unstructured":"Yinan Xu Zihao Yu Dan Tang Guokai Chen et al. 2022. Towards developing high performance RISC-V processors using agile methodology. In MICRO.","key":"e_1_3_2_1_15_1"}],"event":{"sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE","IPSJ","IEEE CAS","IEEE CEDA"],"acronym":"ASPDAC '25","name":"ASPDAC '25: 30th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan"},"container-title":["Proceedings of the 30th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697636","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3658617.3697636","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:49Z","timestamp":1750295869000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697636"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,20]]},"references-count":15,"alternative-id":["10.1145\/3658617.3697636","10.1145\/3658617"],"URL":"https:\/\/doi.org\/10.1145\/3658617.3697636","relation":{},"subject":[],"published":{"date-parts":[[2025,1,20]]},"assertion":[{"value":"2025-03-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}