{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:05:01Z","timestamp":1750309501416,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T00:00:00Z","timestamp":1737331200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","award":["RGPIN-2020-05889"],"award-info":[{"award-number":["RGPIN-2020-05889"]}],"id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007631","name":"Canadian Institute for Advanced Research","doi-asserted-by":"publisher","award":["CIFAR AI Chairs Program"],"award-info":[{"award-number":["CIFAR AI Chairs Program"]}],"id":[{"id":"10.13039\/100007631","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,1,20]]},"DOI":"10.1145\/3658617.3697719","type":"proceedings-article","created":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T14:23:57Z","timestamp":1741098237000},"page":"1104-1111","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Hardware Synthesizable Exceptions using Continuations"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-4430-595X","authenticated-orcid":false,"given":"Paul","family":"Teng","sequence":"first","affiliation":[{"name":"McGill University, Montreal, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4811-2469","authenticated-orcid":false,"given":"Christophe","family":"Dubach","sequence":"additional","affiliation":[{"name":"McGill University \/ MILA, Montreal, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,3,4]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"[n.d.]. Handel-C Language Reference Manual. https:\/\/web.archive.org\/web\/20100331015609\/http:\/\/www.agilityds.com\/literature\/HandelC_Language_Reference_Manual.pdf. Accessed: 2024-02-23."},{"key":"e_1_3_2_1_2_1","unstructured":"[n. d.]. Kiwi Scientific Acceleration Manual. https:\/\/www.cl.cam.ac.uk\/research\/srg\/han\/hprls\/orangepath\/manual\/kiwic.pdf. Accessed: 2024-02-26."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1869459.1869469"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/214448.214454"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3530775"},{"key":"e_1_3_2_1_6_1","volume-title":"Workshop on Open-Source EDA Technology (WOSET).","author":"Eldridge Schuyler","year":"2021","unstructured":"Schuyler Eldridge, Prithayan Barua, Aliaksei Chapyzhenka, Adam Izraelevitz, Jack Koenig, Chris Lattner, Andrew Lenharth, George Leontiev, Fabian Schuiki, Ram Sunder, et al. 2021. MLIR as hardware compiler infrastructure. In Workshop on Open-Source EDA Technology (WOSET)."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586110"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSRE.2015.7381812"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1291151.1291179"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415781"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983050"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.46"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/800179.810196"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1020887011500"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00060"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/CODESISSS.2015.7331371"},{"key":"e_1_3_2_1_17_1","article-title":"Performance modeling and directives optimization for high-level synthesis on FPGA","volume":"39","author":"Zhao Jieru","year":"2019","unstructured":"Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, and Bingsheng He. 2019. Performance modeling and directives optimization for high-level synthesis on FPGA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 7 (2019).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"}],"event":{"name":"ASPDAC '25: 30th Asia and South Pacific Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE","IPSJ","IEEE CAS","IEEE CEDA"],"location":"Tokyo Japan","acronym":"ASPDAC '25"},"container-title":["Proceedings of the 30th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697719","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3658617.3697719","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:49Z","timestamp":1750295869000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697719"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,20]]},"references-count":17,"alternative-id":["10.1145\/3658617.3697719","10.1145\/3658617"],"URL":"https:\/\/doi.org\/10.1145\/3658617.3697719","relation":{},"subject":[],"published":{"date-parts":[[2025,1,20]]},"assertion":[{"value":"2025-03-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}