{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:05:01Z","timestamp":1750309501829,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T00:00:00Z","timestamp":1737331200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100018537","name":"National Science and Technology Major Project","doi-asserted-by":"publisher","award":["2021ZD0114701"],"award-info":[{"award-number":["2021ZD0114701"]}],"id":[{"id":"10.13039\/501100018537","id-type":"DOI","asserted-by":"publisher"}]},{"name":"State Key Laboratory of Integrated Chips and Systems (SKLICS) open fund"},{"name":"SJTU Explore-X fund"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,1,20]]},"DOI":"10.1145\/3658617.3697725","type":"proceedings-article","created":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T14:23:57Z","timestamp":1741098237000},"page":"1230-1236","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6186-5601","authenticated-orcid":false,"given":"Yichen","family":"Cai","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-1433-2676","authenticated-orcid":false,"given":"Linyu","family":"Zhu","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2374-3953","authenticated-orcid":false,"given":"Xinfei","family":"Guo","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University\/State Key Laboratory of Integrated Chips and Systems (SKLICS), Shanghai, China"}]}],"member":"320","published-online":{"date-parts":[[2025,3,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633327"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"e_1_3_2_1_3_1","volume-title":"IWLS 2005 Benchmarks. https:\/\/iwls.org\/iwls2005\/benchmarks.html","author":"IWLS.","year":"2005","unstructured":"IWLS. 2005. IWLS 2005 Benchmarks. https:\/\/iwls.org\/iwls2005\/benchmarks.html"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960424"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCET.2019.8726883"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323866"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2165716"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2376988"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428022"},{"key":"e_1_3_2_1_10_1","unstructured":"OpenCores. 2024. OpenCores. https:\/\/opencores.org\/"},{"key":"e_1_3_2_1_11_1","unstructured":"OpenRISC. 2024. OpenRISC 1200 implementation. https:\/\/github.com\/openrisc\/or1200"},{"key":"e_1_3_2_1_12_1","volume-title":"Effective and efficient approach for power reduction by using multi-bit flip-flops","author":"Shyu Ya-Ting","year":"2012","unstructured":"Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, and Soon-Jyh Chang. 2012. Effective and efficient approach for power reduction by using multi-bit flip-flops. IEEE transactions on very large scale integration (vlsi) systems 21, 4 (2012), 624--635."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297374"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451955"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3588570"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960423"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2016.7841285"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICGCS.2010.5542978"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2966998"},{"key":"e_1_3_2_1_20_1","volume-title":"LSTP: A Logic Synthesis Timing Predictor. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 728--733","author":"Zheng Haisheng","year":"2024","unstructured":"Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, and Bei Yu. 2024. LSTP: A Logic Synthesis Timing Predictor. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 728--733."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD58817.2023.00057"}],"event":{"name":"ASPDAC '25: 30th Asia and South Pacific Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE","IPSJ","IEEE CAS","IEEE CEDA"],"location":"Tokyo Japan","acronym":"ASPDAC '25"},"container-title":["Proceedings of the 30th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697725","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3658617.3697725","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:49Z","timestamp":1750295869000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697725"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,20]]},"references-count":21,"alternative-id":["10.1145\/3658617.3697725","10.1145\/3658617"],"URL":"https:\/\/doi.org\/10.1145\/3658617.3697725","relation":{},"subject":[],"published":{"date-parts":[[2025,1,20]]},"assertion":[{"value":"2025-03-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}