{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:05:02Z","timestamp":1750309502385,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T00:00:00Z","timestamp":1737331200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,1,20]]},"DOI":"10.1145\/3658617.3697759","type":"proceedings-article","created":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T14:32:21Z","timestamp":1741098741000},"page":"1321-1327","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-3225-161X","authenticated-orcid":false,"given":"Mingjun","family":"Wang","sequence":"first","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/Univ. of Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-0147-6231","authenticated-orcid":false,"given":"Hui","family":"Wang","sequence":"additional","affiliation":[{"name":"CASTEST Co., Ltd., Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8896-8600","authenticated-orcid":false,"given":"Zizhen","family":"Liu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9038-2091","authenticated-orcid":false,"given":"Feng","family":"Gu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/Univ. of Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8513-0792","authenticated-orcid":false,"given":"Jianan","family":"Mu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-4967-3189","authenticated-orcid":false,"given":"Jiaping","family":"Tang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/Univ. of Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-2901-1427","authenticated-orcid":false,"given":"Jun","family":"Gao","sequence":"additional","affiliation":[{"name":"CASTEST Co., Ltd., Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8082-4218","authenticated-orcid":false,"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/Univ. of Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8023-5090","authenticated-orcid":false,"given":"Jing","family":"Ye","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/Univ. of Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0874-814X","authenticated-orcid":false,"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences\/Univ. of Chinese Academy of Sciences\/CASTEST, Beijing, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,3,4]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2018. PoliTo ITC99 (I99T). [Online]. Available: https:\/\/github.com\/cad-polito-it\/I99T."},{"key":"e_1_3_2_1_2_1","unstructured":"2021. OpenXuantie. [Online]. Available: https:\/\/github.com\/T-head-Semi\/."},{"key":"e_1_3_2_1_3_1","unstructured":"2023. Hummingbirdv2 E203 Core and SoC. [Online]. Available: https:\/\/github.com\/riscv-mcu\/e203_hbirdv2."},{"key":"e_1_3_2_1_4_1","unstructured":"2023. Open-source high-performance RISC-V processor. [Online]. Available: https:\/\/github.com\/OpenXiangShan\/XiangShan."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2006.49"},{"key":"e_1_3_2_1_6_1","volume-title":"Badiger","author":"Acharya Pradyumna S.","year":"2020","unstructured":"Pradyumna S. Acharya and Sujatha D. Badiger. 2020. Design for Testability (DFT) for a Chip with Memory and Logic. Recent Trends in Analog Design and Digital Devices 3, 2 (2020). http:\/\/hbrppublication.com\/OJS\/index.php\/RTADDD\/article\/view\/1342"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.31"},{"key":"e_1_3_2_1_8_1","volume-title":"20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)","author":"Ahmed Nisar","year":"2005","unstructured":"Nisar Ahmed and Mohammad Tehranipoor. 2005. Improving transition delay fault coverage using hybrid scan-based technique. In 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05). IEEE, 187--195."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583982"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.8361583"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.251160"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185327"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCIT.2010.5665084"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.8361591"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035361"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059880"},{"key":"e_1_3_2_1_17_1","unstructured":"Madhurima Maddela. [n. d.]. ELEC 7250 SEQUENTIAL PARALLEL FAULT SIMULATOR. ([n.d.])."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2019.8758662"},{"key":"e_1_3_2_1_19_1","unstructured":"Mentor. 2020. Tessent\u00ae Scan and ATPG User's Manual (document revision 18 ed.). Mentor A Siemens Business."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1995.512641"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3028005"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3128446"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.34"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.238615"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041869"},{"key":"e_1_3_2_1_26_1","unstructured":"Synopsys. 2021. TestMAX ATPG and TestMAX Diagnosis User Guide. Synopsys."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295104"},{"volume-title":"VLSI test principles and architectures: design for testability","author":"Wang Laung-Terng","key":"e_1_3_2_1_28_1","unstructured":"Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen. 2006. VLSI test principles and architectures: design for testability. Elsevier."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ITC-Asia62534.2024.10661312"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2010.5491771"}],"event":{"name":"ASPDAC '25: 30th Asia and South Pacific Design Automation Conference","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE","IPSJ","IEEE CAS","IEEE CEDA"],"location":"Tokyo Japan","acronym":"ASPDAC '25"},"container-title":["Proceedings of the 30th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697759","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3658617.3697759","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:50Z","timestamp":1750295870000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3697759"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,20]]},"references-count":30,"alternative-id":["10.1145\/3658617.3697759","10.1145\/3658617"],"URL":"https:\/\/doi.org\/10.1145\/3658617.3697759","relation":{},"subject":[],"published":{"date-parts":[[2025,1,20]]},"assertion":[{"value":"2025-03-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}