{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:22:50Z","timestamp":1780356170042,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":61,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T00:00:00Z","timestamp":1737331200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,1,20]]},"DOI":"10.1145\/3658617.3703135","type":"proceedings-article","created":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T14:32:21Z","timestamp":1741098741000},"page":"294-301","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Toward Advancing 3D-ICs Physical Design: Challenges and Opportunities"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-6297-0646","authenticated-orcid":false,"given":"Xueyan","family":"Zhao","sequence":"first","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2916-0493","authenticated-orcid":false,"given":"Weiguo","family":"Li","sequence":"additional","affiliation":[{"name":"Pengcheng Laboratory, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-3686-4576","authenticated-orcid":false,"given":"Zhisheng","family":"Zeng","sequence":"additional","affiliation":[{"name":"Pengcheng Laboratory, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-1762-479X","authenticated-orcid":false,"given":"Zhipeng","family":"Huang","sequence":"additional","affiliation":[{"name":"Beijing Institute of Open Source Chip, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4045-6806","authenticated-orcid":false,"given":"Biwei","family":"Xie","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7145-9391","authenticated-orcid":false,"given":"Xingquan","family":"Li","sequence":"additional","affiliation":[{"name":"Pengcheng Laboratory, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6565-5276","authenticated-orcid":false,"given":"Yungang","family":"Bao","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,3,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3531437.3539702"},{"key":"e_1_3_2_1_2_1","unstructured":"Alexander Andreev Andrey Nikishin Sergey Gribok Phey-Chuin Tan and Choon-Hun Choo. 2014. Clock Network Fishbone Architecture for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node."},{"key":"e_1_3_2_1_3_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 37--42","author":"Bamberg Lennart","year":"2020","unstructured":"Lennart Bamberg, Alberto Garc\u00eda-Ortiz, Lingjun Zhu, Sai Pentapati, Sung Kyu Lim, et al. 2020. Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 37--42."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967013"},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of the 2024 International Symposium on Physical Design. 125--134","author":"Chang Yao-Wen","year":"2024","unstructured":"Yao-Wen Chang. 2024. Physical Design Challenges in Modern Heterogeneous Integration. In Proceedings of the 2024 International Symposium on Physical Design. 125--134."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.204128"},{"key":"e_1_3_2_1_7_1","volume-title":"International Symposium on Signals, Circuits and Systems. Proceedings, SCS","author":"Chaturvedi Rishi","year":"2004","unstructured":"Rishi Chaturvedi and Jiang Hu. 2004. Buffered clock tree for high quality IC design. In International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003.(Cat. No. 03EX720). IEEE, 381--386."},{"key":"e_1_3_2_1_8_1","volume-title":"2023 60th ACM\/IEEE Design Automation Conference (DAC). IEEE, 1--2.","author":"Chen Yan-Jen","year":"2023","unstructured":"Yan-Jen Chen, Yan-Syuan Chen, Wei-Che Tseng, Cheng-Yu Chiang, Yu-Hsiang Lo, and Yao-Wen Chang. 2023. Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies. In 2023 60th ACM\/IEEE Design Automation Conference (DAC). IEEE, 1--2."},{"key":"e_1_3_2_1_9_1","volume-title":"ACM\/IEEE Design Automation Conference (DAC).","author":"Chen Yan-Jen","year":"2024","unstructured":"Yan-Jen Chen, Cheng-Hsiu Hsieh, Po-Han Su, Shao-Hsiang Chen, and Yao-Wen Chang. 2024. Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes. In ACM\/IEEE Design Automation Conference (DAC)."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/293625.293628"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509633.1509725"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3626958","article-title":"Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing","volume":"29","author":"Dewan Monzurul Islam","year":"2023","unstructured":"Monzurul Islam Dewan, Sheng-En David Lin, and Dae Hyun Kim. 2023. Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing. ACM Transactions on Design Automation of Electronic Systems 29, 1 (2023), 1--28.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"e_1_3_2_1_13_1","volume-title":"Design, Test, and Thermal Management","author":"Franzon Paul D","year":"2019","unstructured":"Paul D Franzon, Erik Jan Marinissen, and Muhannad S Bakir. 2019. Handbook of 3D Integration, Volume 4: Design, Test, and Thermal Management. John Wiley & Sons."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009873"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2209291.2209306"},{"key":"e_1_3_2_1_16_1","first-page":"478","article-title":"Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution","volume":"39","author":"Han Kwangsoo","year":"2018","unstructured":"Kwangsoo Han, Andrew B Kahng, and Jiajia Li. 2018. Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 2 (2018), 478--491.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_17_1","volume-title":"Automation & Test in Europe","author":"Healy Michael B","unstructured":"Michael B Healy and Sung Kyu Lim. 2011. A novel TSV topology for many-tier 3D power-delivery networks. In 2011 Design, Automation & Test in Europe. IEEE, 1--4."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024875"},{"key":"e_1_3_2_1_19_1","volume-title":"Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design. 1--5.","author":"Hu Kai-Shun","year":"2022","unstructured":"Kai-Shun Hu, I-Jye Lin, Yu-Hui Huang, Hao-Yu Chi, Yi-Hsuan Wu, and Chin-Fang Cindy Shen. 2022. 2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical Connections. In Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design. 1--5."},{"key":"e_1_3_2_1_20_1","volume-title":"Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication. In 2007 IEEE Electrical Performance of Electronic Packaging","author":"Huang Gang","unstructured":"Gang Huang, Muhannad Bakir, Azad Naeemi, Howard Chen, and James D Meindl. 2007. Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication. In 2007 IEEE Electrical Performance of Electronic Packaging. IEEE, 205--208."},{"key":"e_1_3_2_1_21_1","volume-title":"On Legalization of Die Bonding Bumps and Pads for 3D ICs","author":"Huang Yen-Hsiang","year":"2024","unstructured":"Yen-Hsiang Huang, Sai Pentapati, Anthony Agnesina, Moritz Brunion, and Sung Kyu Lim. 2024. On Legalization of Die Bonding Bumps and Pads for 3D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024)."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","first-page":"647","DOI":"10.1109\/TVLSI.2009.2038165","article-title":"Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies","volume":"19","author":"Khan Nauman H","year":"2010","unstructured":"Nauman H Khan, Syed M Alam, and Soha Hassoun. 2010. Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, 4 (2010), 647--658.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/3670474.3685957"},{"key":"e_1_3_2_1_24_1","volume-title":"2021 58th ACM\/IEEE Design Automation Conference (DAC). IEEE, 1189--1194","author":"Kim Jinwoo","year":"2021","unstructured":"Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, and Sung Kyu Lim. 2021. Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options. In 2021 58th ACM\/IEEE Design Automation Conference (DAC). IEEE, 1189--1194."},{"key":"e_1_3_2_1_25_1","volume-title":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 486--491","author":"Kim Tak-Yung","year":"2010","unstructured":"Tak-Yung Kim and Taewhan Kim. 2010. Clock tree embedding for 3D ICs. In 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 486--491."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003708"},{"key":"e_1_3_2_1_27_1","volume-title":"Proceedings of the 2016 on International Symposium on Physical Design. 3--10","author":"Knechtel Johann","year":"2016","unstructured":"Johann Knechtel and Jens Lienig. 2016. Physical design automation for 3D chip stacks: challenges and solutions. In Proceedings of the 2016 on International Symposium on Physical Design. 3--10."},{"key":"e_1_3_2_1_28_1","volume-title":"Proceedings of the 2018 International Symposium on Physical Design. 90--97","author":"Ku Bon Woong","year":"2018","unstructured":"Bon Woong Ku, Kyungwook Chang, and Sung Kyu Lim. 2018. Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs. In Proceedings of the 2018 International Symposium on Physical Design. 90--97."},{"key":"e_1_3_2_1_29_1","volume-title":"Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration","author":"Liao Peiyu","year":"2023","unstructured":"Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, and Bei Yu. 2023. Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2023)."},{"key":"e_1_3_2_1_30_1","volume-title":"2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 1--6.","author":"Lin Minghao","year":"2016","unstructured":"Minghao Lin, Heming Sun, and Shinji Kimura. 2016. Power-efficient and slew-aware three dimensional gated clock tree synthesis. In 2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 1--6."},{"key":"e_1_3_2_1_31_1","volume-title":"Proceedings of the 2024 International Symposium on Physical Design. 75--82","author":"Liu Siting","year":"2024","unstructured":"Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, and Martin Wong. 2024. Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. In Proceedings of the 2024 International Symposium on Physical Design. 75--82."},{"key":"e_1_3_2_1_32_1","volume-title":"Proceedings of the 2016 on International Symposium on Physical Design. 11--18","author":"Lu Jingwei","year":"2016","unstructured":"Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, and Chung-Kuan Cheng. 2016. ePlace-3D: Electrostatics based Placement for 3D-ICs. In Proceedings of the 2016 on International Symposium on Physical Design. 11--18."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627665"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3019610"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218582"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/1356802.1356925"},{"key":"e_1_3_2_1_37_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 146--151","author":"Murali Gauthaman","year":"2021","unstructured":"Gauthaman Murali and Sung Kyu Lim. 2021. Heterogeneous 3d ics: Current status and future directions for physical design technologies. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 146--151."},{"key":"e_1_3_2_1_38_1","volume-title":"2010 Symposium on VLSI Technology. IEEE, 219--220","author":"Naito T","year":"2010","unstructured":"T Naito, T Ishida, T Onoduka, M Nishigoori, T Nakayama, Y Ueno, Y Ishimoto, A Suzuki, W Chung, R Madurawe, et al. 2010. World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS. In 2010 Symposium on VLSI Technology. IEEE, 219--220."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3313798"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1109\/TCPMT.2010.2101771","article-title":"PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P\/G TSV Array Model Based on Separated P\/G TSV and Chip-PDN Models","volume":"1","author":"Pak Jun So","year":"2011","unstructured":"Jun So Pak, Joohee Kim, Jonghyun Cho, Kiyeong Kim, Taigon Song, Seungyoung Ahn, Junho Lee, Hyungdong Lee, Kunwoo Park, and Joungho Kim. 2011. PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P\/G TSV Array Model Based on Separated P\/G TSV and Chip-PDN Models. IEEE Transactions on Components, Packaging and Manufacturing Technology 1, 2 (2011), 208--219.","journal-title":"IEEE Transactions on Components, Packaging and Manufacturing Technology"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2560531"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"crossref","first-page":"540","DOI":"10.1109\/TCAD.2014.2387827","article-title":"Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs","volume":"4","author":"Panth Shreepad","year":"2015","unstructured":"Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim. 2015. Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4, 34 (2015), 540--553.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2648839"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"crossref","first-page":"266","DOI":"10.1109\/TCAD.2014.2379645","article-title":"Synthesis of TSV Fault-Tolerant 3-D Clock Trees","volume":"34","author":"Park Heechun","year":"2014","unstructured":"Heechun Park and Taewhan Kim. 2014. Synthesis of TSV Fault-Tolerant 3-D Clock Trees. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 2 (2014), 266--279.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3453480"},{"key":"e_1_3_2_1_46_1","volume-title":"2010 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 387--394","author":"Pathak Mohit","year":"2010","unstructured":"Mohit Pathak, Young-Joon Lee, Thomas Moon, and Sung Kyu Lim. 2010. Through-silicon-via management during 3D physical design: When to add and how many?. In 2010 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 387--394."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3569052.3578925"},{"key":"e_1_3_2_1_48_1","volume-title":"Proceedings of the 39th International Conference on Computer-Aided Design. 1--9.","author":"Kiran Pentapati Sai Surya","year":"2020","unstructured":"Sai Surya Kiran Pentapati, Kyungwook Chang, Vassilios Gerousis, Rwik Sengupta, and Sung Kyu Lim. 2020. Pin-3D: A physical synthesis and post-layout optimization flow for heterogeneous monolithic 3D ICs. In Proceedings of the 39th International Conference on Computer-Aided Design. 1--9."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123038"},{"key":"e_1_3_2_1_50_1","volume-title":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 693--698","author":"Shang Yang","year":"2013","unstructured":"Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan, Xin Zhao, and Sung Kyu Lim. 2013. Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. In 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 693--698."},{"key":"e_1_3_2_1_51_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1740--1745","author":"Thuries Sebastien","year":"2020","unstructured":"Sebastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, and Didier Lattard. 2020. M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1740--1745."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"crossref","first-page":"2131","DOI":"10.1109\/TVLSI.2013.2283800","article-title":"Globally Constrained Locally Optimized 3-D Power Delivery Networks","volume":"22","author":"Todri-Sanial Aida","year":"2013","unstructured":"Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, and Arnaud Virazel. 2013. Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Transactions on very large scale Integration (VLSI) Systems 22, 10 (2013), 2131--2144.","journal-title":"IEEE Transactions on very large scale Integration (VLSI) Systems"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825875"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"crossref","first-page":"359","DOI":"10.1145\/567270.567271","article-title":"UST\/DME: a clock tree router for general skew constraints","volume":"7","author":"Albert Tsao Chung-Wen","year":"2002","unstructured":"Chung-Wen Albert Tsao and Cheng-Kok Koh. 2002. UST\/DME: a clock tree router for general skew constraints. ACM Transactions on Design Automation of Electronic Systems (TODAES) 7, 3 (2002), 359--379.","journal-title":"ACM Transactions on Design Automation of Electronic Systems (TODAES)"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/3439706.3447049"},{"key":"e_1_3_2_1_56_1","volume-title":"2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2654--2657","author":"Wang Sying-Jyan","year":"2013","unstructured":"Sying-Jyan Wang, Cheng-Hao Lin, and Katherine Shu-Min Li. 2013. Synthesis of 3D clock tree with pre-bond testability. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2654--2657."},{"key":"e_1_3_2_1_57_1","volume-title":"2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 1--9.","author":"Zhao Xueyan","year":"2023","unstructured":"Xueyan Zhao, Shijian Chen, Yihang Qiu, Jiangkao Li, Zhipeng Huang, Biwei Xie, Xingquan Li, and Yungang Bao. 2023. iPL-3D: A Novel Bilevel Programming Model for Die-to-Die Placement. In 2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 1--9."},{"key":"e_1_3_2_1_58_1","volume-title":"Analytical Heterogeneous Die-to-Die 3D Placement with Macros. arXiv preprint arXiv:2403.09070","author":"Zhao Yuxuan","year":"2024","unstructured":"Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, and Bei Yu. 2024. Analytical Heterogeneous Die-to-Die 3D Placement with Macros. arXiv preprint arXiv:2403.09070 (2024)."},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3221025"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3439706.3446903"},{"key":"e_1_3_2_1_61_1","volume-title":"2021 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 1--6.","author":"Zhu Lingjun","year":"2021","unstructured":"Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, et al. 2021. Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. In 2021 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 1--6."}],"event":{"name":"ASPDAC '25: 30th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '25","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEICE","IPSJ","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the 30th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3703135","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3658617.3703135","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:17:53Z","timestamp":1750295873000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3658617.3703135"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,20]]},"references-count":61,"alternative-id":["10.1145\/3658617.3703135","10.1145\/3658617"],"URL":"https:\/\/doi.org\/10.1145\/3658617.3703135","relation":{},"subject":[],"published":{"date-parts":[[2025,1,20]]},"assertion":[{"value":"2025-03-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}