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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2024,5,31]]},"abstract":"<jats:p>Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies such as SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84\u00d7 less space and 2.62\u00d7 less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilized Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36\u00d7 and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41\u00d7 and 11%, respectively, compared to baseline MLC LLCs.<\/jats:p>","DOI":"10.1145\/3659102","type":"journal-article","created":{"date-parts":[[2024,4,16]],"date-time":"2024-04-16T15:49:38Z","timestamp":1713282578000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers"],"prefix":"10.1145","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-3343-4062","authenticated-orcid":false,"given":"S.","family":"Sivakumar","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Guwahati, Guwahati, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0314-8778","authenticated-orcid":false,"given":"John","family":"Jose","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Guwahati, Guwahati, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6266-6068","authenticated-orcid":false,"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University - Main Campus, University Park, United States"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,5,3]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2567936"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070830"},{"volume-title":"ARM Cortex-A Series Programmer\u2019s Guide for ARMv7-A","year":"2011","key":"e_1_3_1_4_2","unstructured":"ARM. 2011. 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