{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,24]],"date-time":"2026-04-24T03:54:59Z","timestamp":1777002899499,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":37,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,9]],"date-time":"2024-06-09T00:00:00Z","timestamp":1717891200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100006374","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["502384507"],"award-info":[{"award-number":["502384507"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,10]]},"DOI":"10.1145\/3662010.3663451","type":"proceedings-article","created":{"date-parts":[[2024,5,30]],"date-time":"2024-05-30T10:30:07Z","timestamp":1717065007000},"page":"1-10","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["How to Be Fast and Not Furious: Looking Under the Hood of CPU Cache Prefetching"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1485-140X","authenticated-orcid":false,"given":"Roland","family":"K\u00fchn","sequence":"first","affiliation":[{"name":"TU Dortmund University, Lamarr Institute for Machine, Learning and Artificial Intelligence"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2226-6367","authenticated-orcid":false,"given":"Jan","family":"M\u00fchlig","sequence":"additional","affiliation":[{"name":"TU Dortmund University, Lamarr Institute for Machine, Learning and Artificial Intelligence"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0344-5203","authenticated-orcid":false,"given":"Jens","family":"Teubner","sequence":"additional","affiliation":[{"name":"TU Dortmund University, Lamarr Institute for Machine, Learning and Artificial Intelligence"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,6,9]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"perf_event_open(2) - Linux Manual Page. https:\/\/man7.org\/linux\/man-pages\/man2\/perf_event_open.2.html. Online","year":"2024","unstructured":"[n.d.]. perf_event_open(2) - Linux Manual Page. https:\/\/man7.org\/linux\/man-pages\/man2\/perf_event_open.2.html. Online; last accessed March 20, 2024."},{"key":"e_1_3_2_1_2_1","volume-title":"d.]. Skylake: Intel's Longest Serving Architecture. https:\/\/chipsandcheese.com\/2022\/10\/14\/skylake-intels-longest-serving-architecture\/. Online","year":"2024","unstructured":"[n. d.]. Skylake: Intel's Longest Serving Architecture. https:\/\/chipsandcheese.com\/2022\/10\/14\/skylake-intels-longest-serving-architecture\/. Online; last accessed March 22, 2024."},{"key":"e_1_3_2_1_3_1","volume-title":"Software Optimization Guide for AMD Family 15h Processors. https:\/\/www.amd.com\/content\/dam\/amd\/en\/documents\/archived-tech-docs\/software-optimization-guides\/47414_15h_sw_opt_guide.pdf. Online","author":"Devices Advanced Micro","year":"2024","unstructured":"Advanced Micro Devices. 2014. Software Optimization Guide for AMD Family 15h Processors. https:\/\/www.amd.com\/content\/dam\/amd\/en\/documents\/archived-tech-docs\/software-optimization-guides\/47414_15h_sw_opt_guide.pdf. Online; last accessed March 20, 2024."},{"key":"e_1_3_2_1_4_1","volume-title":"Software Optimization Guide for AMD EPYC\u2122 7003 Processors. https:\/\/www.amd.com\/content\/dam\/amd\/en\/documents\/processor-tech-docs\/software-optimization-guides\/56665.zip. Online","author":"Devices Advanced Micro","year":"2024","unstructured":"Advanced Micro Devices. 2020. Software Optimization Guide for AMD EPYC\u2122 7003 Processors. https:\/\/www.amd.com\/content\/dam\/amd\/en\/documents\/processor-tech-docs\/software-optimization-guides\/56665.zip. Online; last accessed March 20, 2024."},{"key":"e_1_3_2_1_5_1","volume-title":"Software Optimization Guide for the AMD Zen4 Microarchitecture. https:\/\/www.amd.com\/content\/dam\/amd\/en\/documents\/processor-tech-docs\/software-optimization-guides\/57647.zip. Online","author":"Devices Advanced Micro","year":"2024","unstructured":"Advanced Micro Devices. 2023. Software Optimization Guide for the AMD Zen4 Microarchitecture. https:\/\/www.amd.com\/content\/dam\/amd\/en\/documents\/processor-tech-docs\/software-optimization-guides\/57647.zip. Online; last accessed May 05, 2024."},{"key":"e_1_3_2_1_6_1","volume-title":"Proceedings of the 2017 International Symposium on Code Generationand Optimization. ACM, 305--317","author":"Ainsworth Sam","unstructured":"Sam Ainsworth and Timothy M. Jones. 2017. Software prefetching for indirect memory accesses. In Proceedings of the 2017 International Symposium on Code Generationand Optimization. ACM, 305--317. http:\/\/dl.acm.org\/citation.cfm?id=3049865"},{"key":"e_1_3_2_1_7_1","volume-title":"Proceedings of 25th International Conference on Very Large Data Bases. 54--65","author":"Boncz Peter A.","year":"1999","unstructured":"Peter A. Boncz, Stefan Manegold, and Martin L. Kersten. 1999. Database Architecture Optimized for the New Bottleneck: Memory Access. In Proceedings of 25th International Conference on Very Large Data Bases. 54--65. http:\/\/www.vldb.org\/conf\/1999\/P5.pdf"},{"key":"e_1_3_2_1_8_1","volume-title":"31st USENIX Security Symposium. USENIX Association, 3917--3934","author":"Borrello Pietro","year":"2022","unstructured":"Pietro Borrello, Andreas Kogler, Martin Schwarzl, Moritz Lipp, Daniel Gruss, and Michael Schwarz. 2022. \u00c6PIC Leak: Architecturally Leaking Uninitialized Data from the Microarchitecture. In 31st USENIX Security Symposium. USENIX Association, 3917--3934. https:\/\/www.usenix.org\/conference\/usenixsecurity22\/presentation\/borrello"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2004.1319989"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807152"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/3430915.3442440"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3075765"},{"key":"e_1_3_2_1_13_1","volume-title":"Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual. https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/671488. Online","year":"2024","unstructured":"Intel. 2024. Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual. https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/671488. Online; last accessed March 20, 2024."},{"key":"e_1_3_2_1_14_1","volume-title":"Intel\u00ae In-Memory Analytics Accelerator (Intel\u00ae IAA) Architecture Specification. https:\/\/cdrdv2-public.intel.com\/721858\/350295-iaa-specification-R03.pdf. Online","year":"2024","unstructured":"Intel. 2024. Intel\u00ae In-Memory Analytics Accelerator (Intel\u00ae IAA) Architecture Specification. https:\/\/cdrdv2-public.intel.com\/721858\/350295-iaa-specification-R03.pdf. Online; last accessed May 05, 2024."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3492321.3519583"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.14778\/3236187.3236216"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2011.5767867"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.14778\/2856318.2856321"},{"key":"e_1_3_2_1_19_1","first-page":"842","article-title":"Apparatus and method for bus signal termination compensation during detected quiet cycle","volume":"6","author":"Kurts Tsvika","year":"2005","unstructured":"Tsvika Kurts, Zelig Wayner, and Tommy Bojan. 2005. Apparatus and method for bus signal termination compensation during detected quiet cycle. US Patent 6,842,035.","journal-title":"US Patent"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2133382.2133384"},{"key":"e_1_3_2_1_21_1","first-page":"73","article-title":"Optimistic Lock Coupling: A Scalable and Efficient General-Purpose Synchronization Method","volume":"42","author":"Leis Viktor","year":"2019","unstructured":"Viktor Leis, Michael Haubenschild, and Thomas Neumann. 2019. Optimistic Lock Coupling: A Scalable and Efficient General-Purpose Synchronization Method. IEEE Data Eng. Bull. 42, 1 (2019), 73--84.","journal-title":"IEEE Data Eng. Bull."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237190"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445574"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168855"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.14778\/3151113.3151114"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3030207.3030223"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/143365.143488"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3448016.3457268"},{"key":"e_1_3_2_1_29_1","volume-title":"Umbra: A Disk-Based System with In-Memory Performance. In 10th Conference on Innovative Data Systems Research, CIDR. http:\/\/cidrdb.org\/cidr2020\/papers\/p29-neumann-cidr20","author":"Neumann Thomas","unstructured":"Thomas Neumann and Michael J. Freitag. 2020. Umbra: A Disk-Based System with In-Memory Performance. In 10th Conference on Innovative Data Systems Research, CIDR. http:\/\/cidrdb.org\/cidr2020\/papers\/p29-neumann-cidr20.pdf"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.14778\/3149193.3149202"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3329785.3329917"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3576915.3623124"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3319535.3354252"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00087"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00016"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3448016.3457260"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.14778\/3636218.3636240"}],"event":{"name":"SIGMOD\/PODS '24: International Conference on Management of Data","location":"Santiago AA Chile","acronym":"SIGMOD\/PODS '24","sponsor":["SIGMOD ACM Special Interest Group on Management of Data"]},"container-title":["Proceedings of the 20th International Workshop on Data Management on New Hardware"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3662010.3663451","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3662010.3663451","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T18:05:11Z","timestamp":1755972311000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3662010.3663451"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,9]]},"references-count":37,"alternative-id":["10.1145\/3662010.3663451","10.1145\/3662010"],"URL":"https:\/\/doi.org\/10.1145\/3662010.3663451","relation":{},"subject":[],"published":{"date-parts":[[2024,6,9]]},"assertion":[{"value":"2024-06-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}