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In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition. 1\u20136."},{"key":"e_1_3_1_120_2","first-page":"1","volume-title":"Proceedings of the Design Automation & Test in Europe Conference","author":"Kim S.","year":"2006","unstructured":"S. Kim. 2006. Area-efficient error protection for caches. In Proceedings of the Design Automation & Test in Europe Conference. 1\u20136."},{"key":"e_1_3_1_121_2","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2004.1276550"},{"key":"e_1_3_1_122_2","doi-asserted-by":"publisher","DOI":"10.1109\/24.52622"},{"key":"e_1_3_1_123_2","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2006.55"},{"key":"e_1_3_1_124_2","first-page":"132","volume-title":"Proceedings of the International Symposium on Low Power Electronics and Design","author":"Li L.","year":"2004","unstructured":"L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. 2004. Soft error and energy consumption interactions: A data cache perspective. In Proceedings of the International Symposium on Low Power Electronics and Design. 132\u2013137."},{"key":"e_1_3_1_125_2","first-page":"269","volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software","author":"Asadi G. H.","year":"2005","unstructured":"G. H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli. 2005. Balancing performance and reliability in the memory hierarchy. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. 269\u2013279."},{"key":"e_1_3_1_126_2","doi-asserted-by":"publisher","DOI":"10.1145\/1269899.1254884"},{"key":"e_1_3_1_127_2","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118507"},{"key":"e_1_3_1_128_2","doi-asserted-by":"publisher","DOI":"10.1145\/2505012"},{"key":"e_1_3_1_129_2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000066"},{"key":"e_1_3_1_130_2","first-page":"1","volume-title":"Proceedings of the IEEE International Conference on Networking, Architecture and Storage","author":"Azizimazreah A.","year":"2018","unstructured":"A. Azizimazreah, Y. Gu, X. Gu, and L. Chen. 2018. Tolerating soft errors in deep learning accelerators with reliable on-chip memory designs. In Proceedings of the IEEE International Conference on Networking, Architecture and Storage. 1\u201310."},{"key":"e_1_3_1_131_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2884460"},{"key":"e_1_3_1_132_2","volume-title":"Proceedings of the Boston area ARChitecture (BARC) Workshop","author":"Eldridge S.","year":"2015","unstructured":"S. Eldridge and A. Joshi. 2015. Exploiting hidden layer modular redundancy for fault-tolerance in neural network accelerators. In Proceedings of the Boston area ARChitecture (BARC) Workshop."},{"key":"e_1_3_1_133_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2012.2199517"},{"key":"e_1_3_1_134_2","doi-asserted-by":"publisher","DOI":"10.1145\/1513895.1513907"},{"key":"e_1_3_1_135_2","first-page":"37","volume-title":"Proceedings of the 45th Annual IEEE\/ACM International Symposium on Microarchitecture","author":"Jeon H.","year":"2012","unstructured":"H. Jeon and M. Annavaram. 2012. Warped-DMR: Light-weight error detection for GPGPU. In Proceedings of the 45th Annual IEEE\/ACM International Symposium on Microarchitecture. 37\u201347."},{"key":"e_1_3_1_136_2","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665686"},{"key":"e_1_3_1_137_2","first-page":"1","volume-title":"Proceedings of the 54th Annual Design Automation Conference","author":"Gupta M.","year":"2017","unstructured":"M. Gupta, D. Lowell, J. Kalamatianos, S. Raasch, V. Sridharan, D. Tullsen, and R. Gupta. 2017. Compiler techniques to reduce the synchronization overhead of gpu redundant multithreading. In Proceedings of the 54th Annual Design Automation Conference. 1\u20136."},{"key":"e_1_3_1_138_2","first-page":"979","volume-title":"Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE\u201918)","author":"Schorn C.","year":"2018","unstructured":"C. Schorn, A. Guntoro, and G. Ascheid. 2018. Accurate neuron resilience prediction for a flexible reliability management in neural network accelerators. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE\u201918). 979\u2013984."},{"key":"e_1_3_1_139_2","first-page":"169","volume-title":"Proceedings of the 47th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W\u201917)","author":"dos Santos F. F.","year":"2017","unstructured":"F. F. dos Santos, L. Draghetti, L. Weigel, L. Carro, P. Navaux, and P. Rech. 2017. Evaluation and mitigation of soft-errors in neural network-based object detection in three GPU architectures. In Proceedings of the 47th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W\u201917). 169\u2013176."},{"key":"e_1_3_1_140_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2823786"},{"key":"e_1_3_1_141_2","doi-asserted-by":"publisher","DOI":"10.1145\/3210559"},{"key":"e_1_3_1_142_2","first-page":"842","volume-title":"Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC\u201918)","author":"Mahmoud A.","year":"2018","unstructured":"A. Mahmoud, S. K. S. Hari, M. B. Sullivan, T. Tsai, and S. W. Keckler. 2018. Optimizing software-directed instruction replication for gpu error detection. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC\u201918). 842\u2013854."},{"key":"e_1_3_1_143_2","doi-asserted-by":"publisher","DOI":"10.1145\/3382132"},{"key":"e_1_3_1_144_2","unstructured":"M. Lapedus. 2021. The Great Quantum Computing Race. Retrieved August 6 2022 from https:\/\/semiengineering.com\/thegreat-quantum-computing-race\/"},{"key":"e_1_3_1_145_2","unstructured":"E. Gibney. 2020. Quantum Computer Race Intensifies as Alternative Technology Gains Steam. Retrieved August 6 2022 from https:\/\/www.nature.com\/articles\/d41586-020-03237-w"},{"key":"e_1_3_1_146_2","unstructured":"E. Pednault J. Gunnels D. Maslov and J. Gambetta. 2019. On Quantum Supremacy. (October 2019). Retrieved December 23 2023 from https:\/\/www.ibm.com\/quantum\/blog\/on-quantum-supremacy"},{"key":"e_1_3_1_147_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-019-1666-5"},{"key":"e_1_3_1_148_2","volume-title":"What Happens When \u2018If\u2019 Turns to \u2018When\u2019 in Quantum Computing?","author":"Bobier J. F.","year":"2021","unstructured":"J. F. Bobier, M. Langione, E. Tao, and A. Gourevitch. 2021. What Happens When \u2018If\u2019 Turns to \u2018When\u2019 in Quantum Computing? Boston Consulting Group."},{"key":"e_1_3_1_149_2","unstructured":"A. Y. Kitaev. 1995. Quantum measurements and the Abelian stabilizer problem. arXiv:9511026. Retrieved from https:\/\/arXiv.org\/quant-ph\/9511026"},{"key":"e_1_3_1_150_2","doi-asserted-by":"publisher","DOI":"10.1119\/1.1463744"},{"key":"e_1_3_1_151_2","doi-asserted-by":"publisher","DOI":"10.1109\/SFCS.1994.365700"},{"key":"e_1_3_1_152_2","doi-asserted-by":"publisher","DOI":"10.1145\/237814.237866"},{"key":"e_1_3_1_153_2","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.127.180501"},{"issue":"18","key":"e_1_3_1_154_2","doi-asserted-by":"crossref","first-page":"180503","DOI":"10.1103\/PhysRevLett.129.180503","article-title":"Universal parity quantum computing","volume":"129","author":"Fellner M.","year":"2022","unstructured":"M. Fellner, A. Messinger, K. Ender, and W. Lechner. 2022. Universal parity quantum computing. Phys. Rev. Lett. 129, 18 (2022), 180503.","journal-title":"Phys. Rev. Lett."},{"key":"e_1_3_1_155_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-022-35285-3"},{"key":"e_1_3_1_156_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-023-06096-3"},{"key":"e_1_3_1_157_2","doi-asserted-by":"crossref","unstructured":"Y. Wang S. Simsek T. M. Gatterman J. A. Gerber K. Gilmore D. Gresh N. Hewitt C. V. Horst M. Matheny T. Mengle and B. Neyenhuis. 2023. Fault-tolerant one-bit addition with the smallest interesting colour code. arXiv:2309.09893. Retrieved from https:\/\/arxiv.org\/abs\/2309.09893","DOI":"10.1126\/sciadv.ado9024"},{"issue":"9","key":"e_1_3_1_158_2","doi-asserted-by":"crossref","first-page":"1500838","DOI":"10.1126\/sciadv.1500838","article-title":"A quantum annealing architecture with all-to-all connectivity from local interactions","volume":"1","author":"Lechner W.","year":"2015","unstructured":"W. Lechner, P. Hauke, and P. Zoller. 2015. A quantum annealing architecture with all-to-all connectivity from local interactions. Sci. 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In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA\u201919). 224\u2013237."},{"key":"e_1_3_1_162_2","unstructured":"IBM. 2018. IBMQ Backend Information. Retrieved November 1 2018 from https:\/\/github.com\/Qiskit\/ibmq-deviceinformation"},{"issue":"3","key":"e_1_3_1_163_2","doi-asserted-by":"crossref","first-page":"034050","DOI":"10.1103\/PhysRevApplied.10.034050","article-title":"Parametrically activated entangling gates using transmon qubits","volume":"10","author":"Caldwell S. A.","year":"2018","unstructured":"S. A. Caldwell, N. Didier, C. A. Ryan, E. A. Sete, A. Hudson, P.Karalekas, R. Manenti, M. P. da Silva, R. Sinclair, E. Acala, and N. Alidoust. 2018. Parametrically activated entangling gates using transmon qubits. Phys. Rev. Appl. 10, 3 (2018), 034050.","journal-title":"Phys. Rev. Appl."},{"key":"e_1_3_1_164_2","doi-asserted-by":"publisher","DOI":"10.1038\/nature18648"},{"key":"e_1_3_1_165_2","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322273"},{"key":"e_1_3_1_166_2","unstructured":"IBM. 2018. IBM Qiskit. Retrieved August 5 2018 from https:\/\/qiskit.org\/"},{"key":"e_1_3_1_167_2","unstructured":"Rigetti. 2018. PyQuil. Retrieved August 1 2018 from https:\/\/github.com\/rigetticomputing\/pyquil"},{"key":"e_1_3_1_168_2","unstructured":"Google. 2018. A Preview of Bristlecone Google's New Quantum Processor. Retrieved August 05 2018 from https:\/\/ai.googleblog.com\/2018\/03\/a-preview-of-bristlecone-googles-new.html"},{"key":"e_1_3_1_169_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00079"},{"key":"e_1_3_1_170_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41567-021-01432-8"},{"key":"e_1_3_1_171_2","first-page":"137","volume-title":"Proceedings of the 52nd Annual IEEE\/IFIP International Conference on Dependable Systems and Networks","author":"Oliveira D.","year":"2022","unstructured":"D. Oliveira, E. Giusto, E. Dri, N. Casciola, B. Baheri, Q. Guan, B. Montrucchio, and P. Rech. 2022. Qufi: A quantum fault injector to measure the reliability of qubits and quantum circuits. In Proceedings of the 52nd Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 137\u2013149."},{"key":"e_1_3_1_172_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-03588-y"},{"issue":"10","key":"e_1_3_1_173_2","doi-asserted-by":"crossref","first-page":"431","DOI":"10.1016\/0042-6989(93)90049-3","article-title":"Michelson contrast, RMS contrast and energy of various spatial stimuli at threshold","volume":"33","author":"Kukkonen H.","year":"1993","unstructured":"H. Kukkonen, J. Rovamo, K. Tiippana, and R. N\u00e4s\u00e4nen. 1993. Michelson contrast, RMS contrast and energy of various spatial stimuli at threshold. Vision Res. 33, 10 (1993), 431\u20131436.","journal-title":"Vision Res."},{"key":"e_1_3_1_174_2","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.32.3266"},{"key":"e_1_3_1_175_2","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.52.R2493"},{"key":"e_1_3_1_176_2","unstructured":"D. Gottesman. 1997. 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