{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:13:42Z","timestamp":1781194422590,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,6,19]],"date-time":"2024-06-19T00:00:00Z","timestamp":1718755200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,6,19]]},"DOI":"10.1145\/3665283.3665292","type":"proceedings-article","created":{"date-parts":[[2024,6,17]],"date-time":"2024-06-17T18:28:00Z","timestamp":1718648880000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Enabling high-level parallel programming on multi-FPGA clusters"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7427-9118","authenticated-orcid":false,"given":"Juan Miguel","family":"de Haro Ruiz","sequence":"first","affiliation":[{"name":"Computer Sciences, Barcelona Supercomputing Center, Spain and Computer Architecture, Universitat Polit\u00e8cnica de Catalunya, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0536-5183","authenticated-orcid":false,"given":"Carlos","family":"\u00c1varez Mart\u00ednez","sequence":"additional","affiliation":[{"name":"Computer Sciences, Barcelona Supercomputing Center, Spain and Computer Architecture, Universitat Polit\u00e8cnica de Catalunya, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6064-7883","authenticated-orcid":false,"given":"Daniel","family":"Jim\u00e9nez-Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Computer Sciences, Barcelona Supercomputing Center, Spain and Computer Architecture, Universitat Polit\u00e8cnica de Catalunya, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0417-3430","authenticated-orcid":false,"given":"Xavier","family":"Martorell Bofill","sequence":"additional","affiliation":[{"name":"Computer Sciences, Barcelona Supercomputing Center, Spain and Computer Architecture, Universitat Polit\u00e8cnica de Catalunya, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,6,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"AMD 2024. UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203). AMD. https:\/\/docs.amd.com\/r\/en-US\/pg203-cmac-usplus\/UltraScale-Devices-Integrated-100G-Ethernet-Subsystem-v3.1-LogiCORE-IP-Product-Guide."},{"key":"e_1_3_2_1_2_1","volume-title":"APEIRON: a Framework for High Level Programming of Dataflow Applications on Multi-FPGA Systems. In 26TH International Conference on Computing in High Energy & Nuclear Physics (CHEP","author":"Ammendola Roberto","year":"2023","unstructured":"Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Francesca\u00a0Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier\u00a0Stanislao Paolucci, 2023. APEIRON: a Framework for High Level Programming of Dataflow Applications on Multi-FPGA Systems. In 26TH International Conference on Computing in High Energy & Nuclear Physics (CHEP 2023)."},{"key":"e_1_3_2_1_3_1","volume-title":"Retrieved","year":"2024","unstructured":"blas 2024. Basic Linear Algebra Subprograms. Retrieved March 26, 2024 from https:\/\/www.netlib.org\/blas"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3506713"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/DCIS58620.2023.10335994"},{"key":"e_1_3_2_1_6_1","volume-title":"MareNostrum supercomputer","author":"Barcelona\u00a0Supercomputing Center","year":"2024","unstructured":"Barcelona\u00a0Supercomputing Center. 2024. MareNostrum supercomputer. Barcelona Supercomputing Center. Retrieved March 31, 2024 from https:\/\/www.bsc.es\/marenostrum\/marenostrum"},{"key":"e_1_3_2_1_7_1","volume-title":"Retrieved","year":"2024","unstructured":"cholesky-github 2024. OmpSs@FPGA distributed Cholesky benchmark. Retrieved May 17, 2024 from https:\/\/github.com\/bsc-pm-ompss-at-fpga\/distributed_Cholesky"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3086106"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS53621.2022.00085"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/H2RC54759.2021.00009"},{"key":"e_1_3_2_1_12_1","volume-title":"Retrieved","year":"2024","unstructured":"heat-github 2024. OmpSs@FPGA distributed Heat benchmark. Retrieved May 17, 2024 from https:\/\/github.com\/bsc-pm-ompss-at-fpga\/distributed_Heat"},{"key":"e_1_3_2_1_13_1","volume-title":"HLS 2024","author":"Intel","year":"2024","unstructured":"Intel HLS 2024. Intel HLS compiler. Retrieved March 25, 2024 from https:\/\/www.intel.com\/content\/www\/us\/en\/software\/programmable\/quartus-prime\/hls-compiler.html"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Torben Kalkhof Carsten Heinz and Andreas Koch. 2024. Enabling FPGA and\u00a0AI Engine Tasks in\u00a0the\u00a0HPX Programming Framework for\u00a0Heterogeneous High-Performance Computing. In Applied Reconfigurable Computing. Architectures Tools and Applications Iouliia Skliarova Piedad Brox\u00a0Jim\u00e9nez M\u00e1rio V\u00e9stias and Pedro\u00a0C. Diniz (Eds.). Springer Nature Switzerland Cham 75\u201389.","DOI":"10.1007\/978-3-031-55673-9_6"},{"key":"e_1_3_2_1_15_1","volume-title":"Retrieved","author":"MEEP","year":"2024","unstructured":"MEEP 2024. MareNostrum Exascale Emulation Platform project website. Retrieved March 21, 2024 from https:\/\/meep-project.eu"},{"key":"e_1_3_2_1_16_1","unstructured":"Message Passing Interface Forum 2021. MPI: A Message-Passing Interface Standard Version 4.0. Message Passing Interface Forum. https:\/\/www.mpi-forum.org\/docs\/mpi-4.0\/mpi40-report.pdf"},{"key":"e_1_3_2_1_17_1","volume-title":"Retrieved","year":"2024","unstructured":"N-body-github 2024. OmpSs@FPGA distributed N-body benchmark. Retrieved May 17, 2024 from https:\/\/github.com\/bsc-pm-ompss-at-fpga\/distributed_N-body"},{"key":"e_1_3_2_1_18_1","volume-title":"Retrieved","year":"2024","unstructured":"OmpSs-2 2024. OmpSs-2 documentation and code. Retrieved March 21, 2024 from https:\/\/pm.bsc.es\/ompss-2"},{"key":"e_1_3_2_1_19_1","volume-title":"Retrieved","year":"2024","unstructured":"ompss-fpga-github 2024. OmpSs@FPGA toolchain repository. Retrieved May 17, 2024 from https:\/\/github.com\/bsc-pm-ompss-at-fpga"},{"key":"e_1_3_2_1_20_1","unstructured":"OmpSs@FPGA. 2024. Accelerator Integrator Tool (AIT). OmpSs@FPGA. https:\/\/github.com\/bsc-pm-ompss-at-fpga\/ait"},{"key":"e_1_3_2_1_21_1","volume-title":"Retrieved","year":"2024","unstructured":"OmpSs@FPGA 2024. OmpSs@FPGA webpage. Retrieved March 25, 2024 from https:\/\/pm.bsc.es\/ompss-at-fpga"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3642921.3642928"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00054"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00051"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2023.3288431"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3578178.3579341"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC49654.2021.9622807"},{"key":"e_1_3_2_1_28_1","volume-title":"HLS 2024","author":"Vitis","year":"2024","unstructured":"Vitis HLS 2024. AMD Vitis HLS tool. Retrieved March 25, 2024 from https:\/\/www.xilinx.com\/products\/design-tools\/vitis\/vitis-hls.html"}],"event":{"name":"HEART 2024: 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","location":"Porto Portugal","acronym":"HEART 2024"},"container-title":["14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 24))"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3665283.3665292","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3665283.3665292","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T19:38:00Z","timestamp":1756237080000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3665283.3665292"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,19]]},"references-count":28,"alternative-id":["10.1145\/3665283.3665292","10.1145\/3665283"],"URL":"https:\/\/doi.org\/10.1145\/3665283.3665292","relation":{},"subject":[],"published":{"date-parts":[[2024,6,19]]},"assertion":[{"value":"2024-06-19","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}